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order this document by mc68331ts/d rev. 2 ?motorola inc.,1993, 1996 this document contains information on a new product. speci?ations and information herein are subject to change without notice. motorola semiconductor technical data mc68331 technical summary 32-bit modular microcontroller 1 introduction the mc68331, a highly-integrated 32-bit microcontroller, combines high-performance data manipula- tion capabilities with powerful peripheral subsystems. the mcu is built up from standard modules that interface through a common intermodule bus (imb). standardization facilitates rapid development of devices tailored for specific applications. the mcu incorporates a 32-bit cpu (cpu32), a system integration module (sim), a general-purpose timer (gpt), and a queued serial module (qsm). the mcu can either synthesize an internal clock signal from an external reference or use an external clock input directly. operation with a 32.768-khz reference frequency is standard. the maximum sys- tem clock speed is 20.97 mhz. because mcu operation is fully static, register and memory contents are not affected by a loss of clock. high-density complementary metal-oxide semiconductor (hcmos) architecture makes the basic power consumption of the mcu low. power consumption can be minimized by stopping the system clock. the cpu32 instruction set includes a low-power stop (lpstop) command that efficiently implements this capability.
motorola mc68331 2 mc68331ts/d table 1 ordering information package type temperature frequency (mhz) package order quantity order number 132-pin pqfp ?0 to +85 c 16 mhz 2 pc tray spakmc331cfc16 36 pc tray mc68331cfc16 20 mhz 2 pc tray spakmc331cfc20 36 pc tray mc68331cfc20 ?0 to +105 c 16 mhz 2 pc tray spakmc331vfc16 36 pc tray mc68331vfc16 20 mhz 2 pc tray spakmc331vfc20 36 pc tray mc68331vfc20 ?0 to +125 c 16 mhz 2 pc tray spakmc331mfc16 36 pc tray mc68331mfc16 20 mhz 2 pc tray spakmc331mfc20 36 pc tray mc68331mfc20 144-pin qfp ?0 to +85 c 16 mhz 2 pc tray spakmc331cfv16 44 pc tray mc68331cfv16 20 mhz 2 pc tray spakmc331cfv20 44 pc tray mc68331cfv20 ?0 to +105 c 16 mhz 2 pc tray spakmc331vfv16 44 pc tray mc68331vfv16 20 mhz 2 pc tray spakmc331vfv20 44 pc tray mc68331vfv20 ?0 to +125 c 16 mhz 2 pc tray spakmc331mfv16 44 pc tray mc68331mfv16 20 mhz 2 pc tray spakmc331mfv20 44 pc tray mc68331mfv20
section page mc68331 motorola mc68331ts/d 3 1 introduction 1 1.1 features ...................................................................................................................................... 4 1.2 block diagram ............................................................................................................................. 5 1.3 pin assignments .......................................................................................................................... 6 1.4 address map ............................................................................................................................... 8 1.5 intermodule bus .......................................................................................................................... 8 2 signal descriptions 9 2.1 pin characteristics ...................................................................................................................... 9 2.2 mcu power connections .......................................................................................................... 10 2.3 mcu driver types ..................................................................................................................... 10 2.4 signal characteristics ................................................................................................................ 10 2.5 signal function .......................................................................................................................... 11 3 system integration module 14 3.1 overview ................................................................................................................................... 14 3.2 system configuration and protection ........................................................................................ 16 3.3 system clock ............................................................................................................................ 21 3.4 external bus interface ............................................................................................................... 24 3.5 chip selects .............................................................................................................................. 28 3.6 general-purpose input/output .................................................................................................. 35 3.7 resets ....................................................................................................................................... 37 3.8 interrupts ................................................................................................................................... 39 3.9 factory test block ..................................................................................................................... 41 4 central processor unit 43 4.1 overview ................................................................................................................................... 43 4.2 programming model .................................................................................................................. 43 4.3 status register .......................................................................................................................... 45 4.4 data types ................................................................................................................................ 45 4.5 addressing modes ..................................................................................................................... 45 4.6 instruction set summary ........................................................................................................... 46 4.7 background debugging mode ................................................................................................... 50 5 queued serial module 51 5.1 overview ................................................................................................................................... 51 5.2 pin function .............................................................................................................................. 52 5.3 qsm registers .......................................................................................................................... 53 5.4 qspi submodule ....................................................................................................................... 56 5.5 sci submodule ......................................................................................................................... 64 6 general-purpose timer module 70 6.1 overview ................................................................................................................................... 70 6.2 capture/compare unit .............................................................................................................. 71 6.3 pulse-width modulator .............................................................................................................. 74 6.4 gpt registers ........................................................................................................................... 75 7 summary of changes 82 table of contents
motorola mc68331 4 mc68331ts/d 1.1 features ?modular architecture ?central processing unit (cpu32) ?upward object code compatible ?new instructions for controller applications ?32-bit architecture ?virtual memory implementation ?loop mode of instruction execution ?table lookup and interpolate instruction ?improved exception handling for controller applications ?trace on change of flow ?hardware breakpoint signal, background mode ?fully static operation ?system integration module (sim) ?external bus support ?programmable chip-select outputs ?system protection logic ?watchdog timer, clock monitor, and bus monitor ?system protection logic ?system clock based on 32.768-khz crystal for low power operation ?test/debug submodule for factory/user test and development ?queued serial module (qsm) ?enhanced serial communication interface (sci), universal asynchronous receiver transmit- ter (uart): modulus baud rate, parity ?queued serial peripheral interface (qspi): 80-byte ram, up to 16 automatic transfers ?dual function i/o ports ?continuous cycling, 8 to 16 bits per transfer ?general-purpose timer (gpt) ?two 16-bit free-running counters with one nine-stage prescaler ?three input capture channels ?four output compare channels ?one input capture/output compare channel ?one pulse accumulator/event counter input ?two pulse-width modulation outputs ?optional external clock input
mc68331 motorola mc68331ts/d 5 1.2 block diagram figure 1 mcu block diagram 331 block pqs5/pcs2 pqs7/txd pqs4/pcs1 pqs6/pcs3 cpu32 qsm imb gpt pqs0/miso pqs1/mosi pqs2/sck portqs txd pcs2 sck miso mosi control pcs1 pqs3/pcs0/ss pcs0/ss rxd pcs3 control bkpt /dsclk ifetch /dsi ipipe /dso freeze dsi dso dsclk ipipe ifetch bkpt irq[7:1] addr[23:0] control port f control port c fc2 fc1 fc0 bg br bgack modclk addr[23:19] clock ebi cs[10:0] br /cs0 bg /cs1 bgack /cs2 r/w reset halt berr clkout xtal extal chip selects csboot addr[18:0] data[15:0] data[15:0] quot test freeze/quot tsc control tsc pc0/fc0/cs3 pc1/fc1/cs4 pc2/fc2/cs5 pc3/addr19/cs6 pc4/addr20/cs7 pc5/addr21/cs8 pc6/addr22/cs9 addr23/cs10 pf7/irq7 pf6/irq6 pf5/irq5 pf4/irq4 pf3/irq3 pf2/irq2 pf1/irq1 pf0/modclk control port e siz1 pe7/siz1 siz0 pe6/siz0 dsack0 pe0/dsack0 dsack1 pe1/dsack1 avec pe2/avec rmc pe3/rmc ds pe5/ds as pe4/as pgp5/oc3/oc1 pgp7/ic4/oc5/oc1 pgp4/oc2/oc1 pgp6/oc4/oc1 pgp0/ic1 pgp1/ic2 pgp2/ic3 port gp pgp7/ic4/oc5/oc1 pgp5/oc3/oc1 pgp2/ic3 pgp0/ic1 pgp1/ic2 control pgp4/oc2/oc1 pgp3/oc1 pgp3/oc1 pgp6/oc4/oc1 pai pai pclk pclk pwmb pwmb pwma pwma
motorola mc68331 6 mc68331ts/d 1.3 pin assignments figure 2 mc68331 132-pin qfp pin assignments 331 132-pin qfp mc68331 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 data9 data10 data11 data12 data13 data14 data15 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 addr16 addr17 addr18 pqs0/miso pqs1/mosi pqs2/sck pqs3/pcs0/ss pqs4/pcs1 pqs5/pcs2 pqs6/pcs3 data0 data1 data2 data3 data4 data5 data6 data7 data8 v dd v ss v dd pe1/dsack1 pe0/dsack0 pe2/avec pe3/rmc pe5/ds csboot bgack /cs2 bg /cs1 br /cs0 51 17 117 16 15 14 13 12 11 10 9 8 7 6 5 4 3 131 130 129 128 127 126 125 124 123 122 121 120 119 118 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 pqs7/txd rxd ipipe /dso freeze/quot xtal extal xfc clkout pf0/modclk pe7/siz1 pe6/siz0 nc pgp0/ic1 pgp1/ic2 pgp2/ic3 pgp3/oc1 pgp4/oc2/oc1 pgp5/oc3/oc1 nc pgp6/oc4/oc1 pgp7/ic4/oc5/oc1 pai nc nc pwma pwmb pclk nc v ss v dd v ss pc0/fc0/cs3 pc1/fc1/cs4 pc2/fc2/cs5 pc3/addr19/cs6 pc4/addr20/cs7 pc5/addr21/cs8 pc6/addr22/cs9 addr23/cs10 pe4/as r/w pf1/irq1 pf2/irq2 pf3/irq3 pf4/irq4 pf5/irq5 pf6/irq6 pf7/irq7 berr halt reset tsc bkpt /dsclk ifetch /dsi 2 1 132 v ddsyn v ss v ss v dd v ss v dd v ss v dd v ss v ss v dd v dd v ss v dd v dd v ss v ss v dd v ss v ss v ss v dd v dd nc
mc68331 motorola mc68331ts/d 7 figure 3 mc68331 144-pin qfp pin assignments 331 144-pin qfp v ss nc fc0/cs3 fc1/cs4 fc2/cs5 addr19/cs6 addr20/cs7 addr21/cs8 addr22/cs9 addr23/cs10 v dd pclk pwmb pwma nc nc nc nc pai pgp6/oc4 v dd v ss nc pgp5/oc3/oc1 pgp4/oc2/oc1 pgp3/oc1 mc68331 nc pe4/as pe6/siz0 pe7/siz1 r/w pf0/modclk pf1/irq1 pf2/irq2 pf3/irq3 pf4/irq4 pf5/irq5 pf6/irq6 pf7/irq7 berr halt reset clkout nc xfc extal v dd xtal freeze/quot tsc bkpt /dsclk ifetch /dsi ipipe /dso rxd pqs7/txd v ss nc pgp2/ic3 pgp1/ic2 pgp0/ic1 nc nc 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 107 108 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 31 32 33 34 35 36 bgack /cs2 bg/cs1 br/cs0 csboot data0 data1 data2 data3 data4 data5 data6 data7 nc data8 nc data9 data10 nc data11 v ss data12 data13 data14 data15 addr0 pe0/dsack0 pe1/dsack1 pe2/avec pe3/rmc pe5/ds v dd nc addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 v dd v ss addr9 addr10 addr11 addr12 nc nc addr13 addr14 addr15 nc addr16 addr17 addr18 pqs0/miso pqs1/mosi pqs2/sck pqs3/pcs0/ss pqs4/pcs1 pqs5/pcs2 pqs6/pcs3 143 144 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 65 68 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 66 67 69 70 71 72 v ss v dd v ss v dd v ss v dd v dd v ss v ss v dd v ss v ss v dd v dd v ss v dd v ss v ss v dd pgp7/ic4/oc5/oc1
motorola mc68331 8 mc68331ts/d 1.4 address map the following figure is a map of the mcu internal addresses. unimplemented blocks are mapped ex- ternally. figure 4 mcu address map 1.5 intermodule bus the intermodule bus (imb) is a standardized bus developed to facilitate both design and operation of modular microcontrollers. it contains circuitry to support exception processing, address space partition- ing, multiple interrupt levels, and vectored interrupts. the standardized modules in the mcu communi- cate with one another and with external components through the imb. the imb in the mcu uses 24 address and 16 data lines. $yffdff $yffa7f $yff93f $yff900 $yff000 331 address map $yffa00 $yffc00 $yffa80 reserved sim gpt qsm $yffaff $yfffff
mc68331 motorola mc68331ts/d 9 2 signal descriptions 2.1 pin characteristics the following table shows mcu pins and their characteristics. all inputs detect cmos logic levels. all inputs can be put in a high-impedance state, but the method of doing this differs depending upon pin function. refer to table 4 , for a description of output drivers. an entry in the discrete i/o column of ta- ble 2 indicates that a pin has an alternate i/o function. the port designation is given when it applies. refer to the mcu block diagram for information about port organization. table 2 mcu pin characteristics pin mnemonic output driver input synchronized input hysteresis discrete i/o port designation addr23/cs10 /eclk a y n o addr[22:19]/cs[9:6] a y n o pc[6:3] addr[18:0] a y n as b y n i/o pe5 avec b y n i/o pe2 berr by n bg /cs1 b bgack /cs2 b y n bkpt /dsclk y y br /cs0 by n clkout a csboot b data[15:0] 1 aw y n ds b y n i/o pe4 dsack1 b y n i/o pe1 dsack0 b y n i/o pe0 dsi/ifetch ay y dso/ipipe a extal 2 special fc[2:0]/cs[5:3] a y n o pc[2:0] freeze/quot a ic4/oc5 a y y i/o gp4 ic[3:1] a y y i/o gp[7:5] halt bo y n irq[7:1] b y y i/o pf[7:1] miso bo y y i/o pqs0 modclk 1 b y n i/o pf0 mosi bo y y i/o pqs1 oc[4:1] a y y i/o gp[3:0] pai 3 y y i pclk 3 y y i pcs0 /ss bo y y i/o pqs3 pcs[3:1] bo y y i/o pqs[6:4] pwma, pwmb a o r/w ay n reset bo y y rmc b y n i/o pe3
motorola mc68331 10 mc68331ts/d notes: 1. data[15:0] are synchronized during reset only. modclk is synchronized only when used as an input port pin. 2. extal, xfc, and xtal are clock reference connections. 3. pai and pclk can be used for discrete input, but are not part of an i/o port. 2.2 mcu power connections 2.3 mcu driver types 2.4 signal characteristics rxd n n sck bo y y i/o pqs2 siz[1:0] b y n i/o pe[7:6] tsc y y txd bo y y i/o pqs7 xfc 2 special xtal 2 special table 3 mcu power connections v ddsyn clock synthesizer power v sse /v dde external periphery power (source and drain) v ssi /v ddi internal module power (source and drain) table 4 mcu driver types type i/o description a o output-only signals that are always driven; no external pull-up required aw o type a output with weak p-channel pull-up during reset b o three-state output that includes circuitry to pull up output before high impedance is es- tablished, to ensure rapid rise time. an external holding resistor is required to maintain logic level while the pin is in the high-impedance state. bo o type b output that can be operated in an open-drain mode table 5 mcu signal characteristics signal name mcu module signal type active state addr[23:0] sim bus as sim output 0 avec sim input 0 berr sim input 0 bg sim output 0 bgack sim input 0 bkpt cpu32 input 0 br sim input 0 clkout sim output cs[10:0] sim output 0 csboot sim output 0 data[15:0] sim bus ds sim output 0 table 2 mcu pin characteristics (continued) pin mnemonic output driver input synchronized input hysteresis discrete i/o port designation
mc68331 motorola mc68331ts/d 11 2.5 signal function dsack[1:0] sim input 0 dsclk cpu32 input serial clock dsi cpu32 input (serial data) dso cpu32 output (serial data) extal sim input fc[2:0] sim output freeze sim output 1 halt sim input/output 0 ic[4:1] gpt input ifetch cpu32 output ipipe cpu32 output irq[7:1] sim input 0 miso qsm input/output modclk sim input mosi qsm input/output oc[5:1] gpt output pai gpt input pc[6:0] sim output (port) pcs[3:0] qsm input/output pe[7:0] sim input/output (port) pf[7:0] sim input/output (port) pqs[7:0] qsm input/output (port) pclk gpt input pwma, pwmb gpt output quot sim output reset sim input/output 0 rmc sim output 0 r/w sim output 1/0 rxd qsm input sck qsm input/output siz[1:0] sim output ss qsm input 0 tsc sim input txd qsm output xfc sim input xtal sim output table 6 mcu signal function signal name mnemonic function address bus addr[23:0] 24-bit address bus address strobe as indicates that a valid address is on the address bus autovector avec requests an automatic vector during interrupt acknowledge bus error berr indicates that a bus error has occurred bus grant bg indicates that the mcu has relinquished the bus bus grant acknowledge bgack indicates that an external device has assumed bus mastership breakpoint bkpt signals a hardware breakpoint to the cpu bus request br indicates that an external device requires bus mastership system clockout clkout system clock output chip selects cs[10:0] select external devices at programmed addresses table 5 mcu signal characteristics (continued) signal name mcu module signal type active state
motorola mc68331 12 mc68331ts/d boot chip select csboot chip select for external boot startup rom data bus data[15:0] 16-bit data bus data strobe ds during a read cycle, indicates when it is possible for an external device to place data on the data bus. during a write cycle, indi- cates that valid data is on the data bus. data and size acknowledge dsack[1:0] provide asynchronous data transfers and dynamic bus sizing development serial in, out, clock dsi, dso, dsclk serial i/o and clock for background debugging mode crystal oscillator extal, xtal connections for clock synthesizer circuit reference; a crystal or an external oscillator can be used function codes fc[2:0] identify processor state and current address space freeze freeze indicates that the cpu has entered background mode halt halt suspend external bus activity input capture ic[3:1] when a specified transition is detected on an input capture pin, the value in an internal gpt counter is latched input capture 4/output compare 5 ic4/oc5 can be configured for either an input capture or output compare instruction pipeline ipipe , ifetch indicate instruction pipeline activity interrupt request level irq[7:1] provides an interrupt priority level to the cpu master in slave out miso serial input to qspi in master mode; serial output from qspi in slave mode clock mode select modclk selects the source and type of system clock master out slave in mosi serial output from qspi in master mode; serial input to qspi in slave mode output compare oc[5:1] change state when the value of an internal gpt counter matches a value stored in a gpt control register pulse accumulator input pai signal input to the pulse accumulator port c pc[6:0] sim digital output port signals auxiliary timer clock input pclk external clock dedicated to the gpt peripheral chip select pcs[3:0] qspi peripheral chip selects port e pe[7:0] sim digital i/o port signals port f pf[7:0] sim digital i/o port signals port qs pqs[7:0] qsm digital i/o port signals pulse-width modulation pwma, pwmb output for pwm quotient out quot provides the quotient bit of the polynomial divider reset reset system reset read-modify-write cycle rmc indicates an indivisible read-modify-write instruction read/write r/w indicates the direction of data transfer on the bus sci receive data rxd serial input to the sci qspi serial clock sck clock output from qspi in master mode; clock input to qspi in slave mode size siz[1:0] indicates the number of bytes to be transferred during a bus cycle slave select ss causes serial transmission when qspi is in slave mode; causes mode fault in master mode three-state control tsc places all output drivers in a high-impedance state sci transmit data txd serial output from the sci external filter capacitor xfc connection for external phase-locked loop filter capacitor table 6 mcu signal function (continued) signal name mnemonic function
mc68331 motorola mc68331ts/d 13
motorola mc68331 14 mc68331ts/d 3 system integration module the system integration module (sim) consists of five functional blocks that control system start-up, ini- tialization, configuration, and external bus. figure 5 sim block diagram 3.1 overview the system configuration and protection block controls mcu configuration and operating mode. the block also provides bus and software watchdog monitors. the system clock generates clock signals used by the sim, other imb modules, and external devices. in addition, a periodic interrupt generator supports execution of time-critical control routines. the external bus interface handles the transfer of information between imb modules and external ad- dress space. the chip-select block provides eleven general-purpose chip-select signals and a boot rom chip-select signal. both general-purpose and boot rom chip-select signals have associated base address regis- ters and option registers. the system test block incorporates hardware necessary for testing the mcu. it is used to perform fac- tory tests, and its use in normal applications is not supported. the sim control register address map occupies 128 bytes. unused registers within the 128-byte ad- dress space return zeros when read. the ?ccess?column in the sim address map below indicates which registers are accessible only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege level, according to the value of the supv bit in the simcr. 300 s(c)im block system configuration clock synthesizer chip selects external bus interface factory test clkout extal modclk chip selects external bus reset tsc freeze/quot xtal system protection
mc68331 motorola mc68331ts/d 15 table 7 sim address map access address 15 8 7 0 s $yffa00 sim configuration (simcr) s $yffa02 factory test (simtr) s $yffa04 clock synthesizer control (syncr) s $yffa06 not used reset status register (rsr) s $yffa08 module test e (simtre) s $yffa0a not used not used s $yffa0c not used not used s $yffa0e not used not used s/u $yffa10 not used port e data (porte0) s/u $yffa12 not used port e data (porte1) s/u $yffa14 not used port e data direction (ddre) s $yffa16 not used port e pin assignment (pepar) s/u $yffa18 not used port f data (portf0) s/u $yffa1a not used port f data (portf1) s/u $yffa1c not used port f data direction (ddrf) s $yffa1e not used port f pin assignment (pfpar) s $yffa20 not used system protection control (sypcr) s $yffa22 periodic interrupt control (picr) s $yffa24 periodic interrupt timing (pitr) s $yffa26 not used software service (swsr) s $yffa28 not used not used s $yffa2a not used not used s $yffa2c not used not used s $yffa2e not used not used s $yffa30 test module master shift a (tstmsra) s $yffa32 test module master shift b (tstmsrb) s $yffa34 test module shift count (tstsc) s $yffa36 test module repetition counter (tstrc) s $yffa38 test module control (creg) s/u $yffa3a test module distributed register (dreg) $yffa3c not used not used $yffa3e not used not used s/u $yffa40 not used port c data (portc) $yffa42 not used not used s $yffa44 chip-select pin assignment (cspar0) s $yffa46 chip-select pin assignment (cspar1) s $yffa48 chip-select base boot (csbarbt) s $yffa4a chip-select option boot (csorbt) s $yffa4c chip-select base 0 (csbar0) s $yffa4e chip-select option 0 (csor0) s $yffa50 chip-select base 1 (csbar1) s $yffa52 chip-select option 1 (csor1) s $yffa54 chip-select base 2 (csbar2) s $yffa56 chip-select option 2 (csor2) s $yffa58 chip-select base 3 (csbar3) s $yffa5a chip-select option 3 (csor3) s $yffa5c chip-select base 4 (csbar4)
motorola mc68331 16 mc68331ts/d y = m111, where m is the logic state of the module mapping (mm) bit in the simcr. 3.2 system configuration and protection this functional block provides configuration control for the entire mcu. it also performs interrupt arbi- tration, bus monitoring, and system test functions. mcu system protection includes a bus monitor, a halt monitor, a spurious interrupt monitor, and a software watchdog timer. these functions have been made integral to the microcontroller to reduce the number of external components in a complete control system. s $yffa5e chip-select option 4 (csor4) s $yffa60 chip-select base 5 (csbar5) s $yffa62 chip-select option 5 (csor5) s $yffa64 chip-select base 6 (csbar6) s $yffa66 chip-select option 6 (csor6) s $yffa68 chip-select base 7 (csbar7) s $yffa6a chip-select option 7 (csor7) s $yffa6c chip-select base 8 (csbar8) s $yffa6e chip-select option 8 (csor8) s $yffa70 chip-select base 9 (csbar9) s $yffa72 chip-select option 9 (csor9) s $yffa74 chip-select base 10 (csbar10) s $yffa76 chip-select option 10 (csor10) $yffa78 not used not used $yffa7a not used not used $yffa7c not used not used $yffa7e not used not used table 7 sim address map (continued) access address 15 8 7 0
mc68331 motorola mc68331ts/d 17 figure 6 system configuration and protection block 3.2.1 system configuration the sim controls mcu configuration during normal operation and during internal testing. the sim configuration register controls system configuration. it can be read or written at any time, ex- cept for the module mapping (mm) bit, which can be written only once. exoff ?xternal clock off 0 = the clkout pin is driven from an internal clock source. 1 = the clkout pin is placed in a high-impedance state. frzsw ?reeze software enable 0 = when freeze is asserted, the software watchdog and periodic interrupt timer counters con- tinue to run. 1 = when freeze is asserted, the software watchdog and periodic interrupt timer counters are dis- abled, preventing interrupts during software debug. frzbm ?reeze bus monitor enable 0 = when freeze is asserted, the bus monitor continues to operate. 1 = when freeze is asserted, the bus monitor is disabled. simcr ?im configuration register $yffa00 15 14 13 12 11 10 9 8 7 6 5 4 3 0 exoff frzsw frzbm 0 slven 0 shen supv mm 0 0 iarb reset: 0 0 0 0 data11 0 0 0 1 1 0 0 1 1 1 1 300 sys protect block reset status halt monitor bus monitor spurious interrupt monitor software watchdog timer periodic interrupt timer 2 9 prescaler clock irq[7:1] berr reset request reset request
motorola mc68331 18 mc68331ts/d slven ?actory test mode enabled this bit is a read-only status bit that reflects the state of data11 during reset. 0 = imb is not available to an external master. 1 = an external bus master has direct access to the imb. shen[1:0] ?how cycle enable this field determines what the ebi does with the external bus during internal transfer operations. a show cycle allows internal transfers to be externally monitored. the table below shows whether show cycle data is driven externally, and whether external bus arbitration can occur. to prevent bus conflict, external peripherals must not be enabled during show cycles. supv ?upervisor/unrestricted data space the supv bit places the sim global registers in either supervisor or user data space. 0 = registers with access controlled by the supv bit are accessible from either the user or super- visor privilege level. 1 = registers with access controlled by the supv bit are restricted to supervisor access only. mm ?odule mapping 0 = internal modules are addressed from $7ff000 ?7fffff. 1 = internal modules are addressed from $fff000 ?ffffff. iarb[3:0] ?nterrupt arbitration field each module that can generate interrupt requests has an interrupt arbitration (iarb) field. arbitration between interrupt requests of the same priority is performed by serial contention between iarb field bit values. contention must take place whenever an interrupt request is acknowledged, even when there is only a single pending request. an iarb field must have a non-zero value for contention to take place. if an interrupt request from a module with an iarb field value of %0000 is recognized, the cpu pro- cesses a spurious interrupt exception. because the sim routes external interrupt requests to the cpu, the sim iarb field value is used for arbitration between internal and external interrupts of the same pri- ority. the reset value of iarb for the sim is %1111, and the reset iarb value for all other modules is %0000, which prevents sim interrupts from being discarded during initialization. 3.2.2 system protection control register the system protection control register controls system monitor functions, software watchdog clock prescaling, and bus monitor timing. this register can be written only once following power-on or reset, but can be read at any time. swe ?oftware watchdog enable 0 = software watchdog disabled 1 = software watchdog enabled shen action 00 show cycles disabled, external arbitration enabled 01 show cycles enabled, external arbitration disabled 10 show cycles enabled, external arbitration enabled 11 show cycles enabled, external arbitration enabled, internal activity is halted by a bus grant sypcr ?ystem protection control register $yffa21 15 8 7 6 5 4 3 2 1 0 not used swe swp swt hme bme bmt reset: 1 modclk 0 0 0 0 0 0
mc68331 motorola mc68331ts/d 19 swp ?oftware watchdog prescale this bit controls the value of the software watchdog prescaler. 0 = software watchdog clock not prescaled 1 = software watchdog clock prescaled by 512 swt[1:0] ?oftware watchdog timing this field selects the divide ratio used to establish software watchdog time-out period. the following ta- ble gives the ratio for each combination of swp and swt bits. hme ?alt monitor enable 0 = disable halt monitor function 1 = enable halt monitor function bme ?us monitor external enable 0 = disable bus monitor function for an internal to external bus cycle. 1 = enable bus monitor function for an internal to external bus cycle. bmt[1:0] ?us monitor timing this field selects a bus monitor time-out period as shown in the following table. 3.2.3 bus monitor the internal bus monitor checks for excessively long dsack response times during normal bus cycles and for excessively long dsack or avec response times during interrupt acknowledge cycles. the monitor asserts berr if response time is excessive. dsack and avec response times are measured in clock cycles. the maximum allowable response time can be selected by setting the bmt field. the monitor does not check dsack response on the external bus unless the cpu initiates the bus cy- cle. the bme bit in the sypcr enables the internal bus monitor for internal to external bus cycles. if a system contains external bus masters, an external bus monitor must be implemented and the internal to external bus monitor option must be disabled. 3.2.4 halt monitor the halt monitor responds to an assertion of halt on the internal bus. a flag in the reset status register (rsr) indicates that the last reset was caused by the halt monitor. the halt monitor reset can be inhib- ited by the hme bit in the sypcr. swp swt ratio 000 2 9 001 2 11 010 2 13 011 2 15 100 2 18 101 2 20 110 2 22 111 2 24 bmt bus monitor time-out period 00 64 system clocks 01 32 system clocks 10 16 system clocks 11 8 system clocks
motorola mc68331 20 mc68331ts/d 3.2.5 spurious interrupt monitor the spurious interrupt monitor issues berr if no interrupt arbitration occurs during an interrupt-ac- knowledge cycle. 3.2.6 software watchdog the software watchdog is controlled by swe in the sypcr. once enabled, the watchdog requires that a service sequence be written to swsr on a periodic basis. if servicing does not take place, the watch- dog times out and issues a reset. this register can be written at any time, but returns zeros when read. register shown with read value perform a software watchdog service sequence as follows: 1. write $55 to swsr. 2. write $aa to swsr. both writes must occur before time-out in the order listed, but any number of instructions can be exe- cuted between the two writes. the watchdog clock rate is affected by swp and swt in sypcr. when swt[1:0] are modified, a watchdog service sequence must be performed before the new time-out period takes effect. the reset value of swp is affected by the state of the modclk pin on the rising edge of reset, as shown in the following table. 3.2.7 periodic interrupt timer the periodic interrupt timer (pit) generates interrupts of specified priorities at specified intervals. timing for the pit is provided by a programmable prescaler driven by the system clock. this register contains information concerning periodic interrupt priority and vectoring. bits [10:0] can be read or written at any time. bits [15:11] are unimplemented and always return zero. pirql[2:0] ?eriodic interrupt request level the following table shows what interrupt request level is asserted when a periodic interrupt is generat- ed. if a pit interrupt and an external irq signal of the same priority occur simultaneously, the pit in- terrupt is serviced first. the periodic timer continues to run when the interrupt is disabled. swsr ?oftware service register $yffa27 15 8 7 6 5 4 3 2 1 0 not used 0 0 0 0 0 0 0 0 reset: 0 0 0 0 0 0 0 0 modclk swp 01 10 picr ?periodic interrupt control register $yffa22 15 14 13 12 11 10 8 7 0 0 0 0 0 0 pirql piv reset: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
mc68331 motorola mc68331ts/d 21 piv[7:0] ?eriodic interrupt vector the bits of this field contain the vector generated in response to an interrupt from the periodic timer. when the sim responds, the periodic interrupt vector is placed on the bus. the pitr contains the count value for the periodic timer. a zero value turns off the periodic timer. this register can be read or written at any time. ptp ?eriodic timer prescaler control 0 = periodic timer clock not prescaled 1 = periodic timer clock prescaled by a value of 512 the reset state of ptp is the complement of the state of the modclk signal during reset. pitm[7:0] ?eriodic interrupt timing modulus field this is an 8-bit timing modulus. the period of the timer can be calculated as follows: pit period = [(pitm)(prescaler)(4)]/extal where pit period = periodic interrupt timer period pitm = periodic interrupt timer register modulus (pitr[7:0]) extal frequency = crystal frequency prescale = 512 or 1 depending on the state of the ptp bit in the pitr 3.3 system clock the system clock in the sim provides timing signals for the imb modules and for an external peripheral bus. because mcu operation is fully static, register and memory contents are not affected when the clock rate changes. system hardware and software support changes in the clock rate during operation. the system clock signal can be generated in three ways. an internal phase-locked loop can synthesize the clock from an internal or external frequency source, or the clock signal can be input from an external source. following is a block diagram of the clock submodule. pirql interrupt request level 000 periodic interrupt disabled 001 interrupt request level 1 010 interrupt request level 2 011 interrupt request level 3 100 interrupt request level 4 101 interrupt request level 5 110 interrupt request level 6 111 interrupt request level 7 pitr ?eriodic interrupt timer register $yffa24 15 14 13 12 11 10 9 8 7 0 0 0 0 0 0 0 0 ptp pitm reset: 0 0 0 0 0 0 0 modclk 0 0 0 0 0 0 0 0
motorola mc68331 22 mc68331ts/d figure 7 system clock block diagram 3.3.1 clock sources the state of the clock mode (modclk) pin during reset determines the clock source. when modclk is held high during reset, the clock synthesizer generates a clock signal from either a crystal oscillator or an external reference input. clock synthesizer control register syncr determines operating frequen- cy and various modes of operation. when modclk is held low during reset, the clock synthesizer is disabled, and an external system clock signal must be applied. when the synthesizer is disabled, syn- cr control bits have no effect. a reference crystal must be connected between the extal and xtal pins to use the internal oscillator. use of a 32.768-khz crystal is recommended. these crystals are inexpensive and readily available. if an external reference signal or an external system clock signal is applied through the extal pin, the xtal pin must be left floating. external reference signal frequency must be less than or equal to max- imum specified reference frequency. external system clock signal frequency must be less than or equal to maximum specified system clock frequency. when an external system clock signal is applied (i.e., the pll is not used), duty cycle of the input is critical, especially at near maximum operating frequencies. the relationship between clock signal duty cycle and clock signal period is expressed: minimum external clock period = minimum external clock high/low time 50% ?percentage variation of external clock input duty cycle sys clock block 32khz clkout extal phase comparator low-pass filter vco crystal oscillator system clock system clock control xtal xfc pin v ddsyn xfc 0.1 m f 0.01 m f 0.1 m f feedback divider 22 pf 22 pf 10m 330k 1. must be low-leakage capacitor (insulation resistance 30,000 m w or greater). 2. resistance and capacitance based on a test circuit constructed with a daishinku dmx-38 32.768-khz crystal. specific components must be based on crystal type. contact crystal vendor for exact circuit. v ddsyn 22 w x y 1 v ssi v ssi v ssi r3 r4 32.768 khz
mc68331 motorola mc68331ts/d 23 3.3.2 clock synthesizer operation a voltage controlled oscillator (vco) generates the system clock signal. a portion of the clock signal is fed back to a divider/counter. the divider controls the frequency of one input to a phase comparator. the other phase comparator input is a reference signal, either from the internal oscillator or from an external source. the comparator generates a control signal proportional to the difference in phase be- tween its two inputs. the signal is low-pass filtered and used to correct vco output frequency. the synthesizer locks when vco frequency is identical to reference frequency. lock time is affected by the filter time constant and by the amount of difference between the two comparator inputs. whenever comparator input changes, the synthesizer must re-lock. lock status is shown by the slock bit in syn- cr. the mcu does not come out of reset state until the synthesizer locks. crystal type, characteristic fre- quency, and layout of external oscillator circuitry affect lock time. the low-pass filter requires an external low-leakage capacitor, typically 0.1 m f, connected between the xfc and v ddsyn pins. v ddsyn is used to power the clock circuits. a separate power source increases mcu noise immunity and can be used to run the clock when the mcu is powered down. use a quiet power supply as the v ddsyn source, since pll stability depends on the vco, which uses this supply. place adequate ex- ternal bypass capacitors as close as possible to the v ddsyn pin to ensure stable operating frequency. when the clock synthesizer is used, control register syncr determines operating frequency and vari- ous modes of operation. syncr can be read only when the processor is operating at the supervisor privilege level. the syncr x bit controls a divide by two prescaler that is not in the synthesizer feedback loop. setting x doubles clock speed without changing vco speed. there is no vco relock delay. the syncr w bit controls a 3-bit prescaler in the feedback divider. setting w increases vco speed by a factor of four. the syncr y field determines the count modulus for a modulo 64 down counter, causing it to divide by a value of y + 1. when either w or y value changes, there is a vco relock delay. clock frequency is determined by syncr bit settings as follows: f system = f reference [4(y + 1)(2 2w +x )] in order for the device to perform correctly, the clock frequency selected by the w, x, and y bits must be within the limits specified for the mcu. the vco frequency is twice the system clock frequency if x = 1 or four times the system clock frequency if x = 0. the reset state of syncr ($3f00) produces a modulus-64 count. 3.3.3 clock control the clock control circuits determine system clock frequency and clock operation under special circum- stances, such as following loss of synthesizer reference or during low-power operation. clock source is determined by the logic state of the modclk pin during reset. syncr ?lock synthesizer control register $yffa04 15 14 13 8 7 6 5 4 3 2 1 0 w x y ediv 0 0 slimp slock rsten stsim stext reset: 0 0 1 1 1 1 1 1 0 0 0 u u 0 0 0
motorola mc68331 24 mc68331ts/d when the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper byte of syncr. bits in the lower byte show status of or control operation of internal and external clocks. the syncr can be read or written only when the cpu is operating at the supervisor privilege level. w ?requency control (vco) this bit controls a prescaler tap in the synthesizer feedback loop. setting the bit increases the vco speed by a factor of four. vco relock delay is required. x ?requency control bit (prescale) this bit controls a divide by two prescaler that is not in the synthesizer feedback loop. setting the bit doubles clock speed without changing the vco speed. there is no vco relock delay. y[5:0] ?requency control (counter) the y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by a value of y + 1. values range from 0 to 63. vco relock delay is required. ediv ? clock divide rate 0 = eclk frequency is system clock divided by 8. 1 = eclk frequency is system clock divided by 16. eclk is an external m6800 bus clock available on pin addr23. refer to 3.5 chip selects for more in- formation. slimp ?imp mode flag 0 = external crystal is vco reference. 1 = loss of crystal reference. when the on-chip synthesizer is used, loss of reference frequency causes slimp to be set. the vco continues to run using the base control voltage. maximum limp frequency is maximum specified system clock frequency. x-bit state affects limp frequency. slock ?ynthesizer lock flag 0 = vco is enabled, but has not locked. 1 = vco has locked on the desired frequency (or system clock is external). the mcu maintains reset state until the synthesizer locks, but slock does not indicate synthesizer lock status until after the user writes to syncr. rsten ?eset enable 0 = loss of crystal causes the mcu to operate in limp mode. 1 = loss of crystal causes system reset. stsim ?top mode sim clock 0 = when lpstop is executed, the sim clock is driven from the crystal oscillator and the vco is turned off to conserve power. 1 = when lpstop is executed, the sim clock is driven from the vco. stext ?top mode external clock 0 = when lpstop is executed, the clkout signal is held negated to conserve power. 1 = when lpstop is executed, the clkout signal is driven from the sim clock, as determined by the state of the stsim bit. 3.4 external bus interface the external bus interface (ebi) transfers information between the internal mcu bus and external de- vices. the external bus has 24 address lines and 16 data lines. the ebi provides dynamic sizing between 8-bit and 16-bit data accesses. it supports byte, word, and long-word transfers. ports are accessed through the use of asynchronous cycles controlled by the data transfer (siz1 and siz0) and data size acknowledge pins (dsack1 and dsack0 ). multiple bus cycles may be required for a transfer to or from an 8-bit port.
mc68331 motorola mc68331ts/d 25 port width is the maximum number of bits accepted or provided during a bus transfer. external devices must follow the handshake protocol described below. control signals indicate the beginning of the cycle, the address space, the size of the transfer, and the type of cycle. the selected device controls the length of the cycle. strobe signals, one for the address bus and another for the data bus, indicate the validity of an address and provide timing information for data. the ebi operates in an asynchronous mode for any port width. to add flexibility and minimize the necessity for external logic, mcu chip-select logic can be synchro- nized with ebi transfers. chip-select logic can also provide internally-generated bus control signals for these accesses. refer to 3.5 chip selects for more information. 3.4.1 bus control signals the cpu initiates a bus cycle by driving the address, size, function code, and read/write outputs. at the beginning of the cycle, size signals siz0 and siz1 are driven along with the function code signals. the size signals indicate the number of bytes remaining to be transferred during an operand cycle. they are valid while the address strobe (as ) is asserted. the following table shows siz0 and siz1 encoding. the read/write (r/w ) signal determines the direction of the transfer during a bus cycle. this signal changes state, when required, at the beginning of a bus cycle, and is valid while as is asserted. r/w only chang- es state when a write cycle is preceded by a read cycle or vice versa. the signal can remain low for two consecutive write cycles. 3.4.2 function codes the cpu32 automatically generates function code signals fc[2:0]. the function codes can be consid- ered address extensions that automatically select one of eight address spaces to which an address ap- plies. these spaces are designated as either user or supervisor, and program or data spaces. address space 7 is designated cpu space. cpu space is used for control information not normally associated with read or write bus cycles. function codes are valid while as is asserted. 3.4.3 address bus address bus signals addr[23:0] define the address of the most significant byte to be transferred during a bus cycle. the mcu places the address on the bus at the beginning of a bus cycle. the address is valid while as is asserted. table 8 size signal encoding siz1 siz0 transfer size 0 1 byte 1 0 word 1 1 three byte 0 0 long word table 9 cpu32 address space encoding fc2 fc1 fc0 address space 0 0 0 reserved 0 0 1 user data space 0 1 0 user program space 0 1 1 reserved 1 0 0 reserved 1 0 1 supervisor data space 1 1 0 supervisor program space 1 1 1 cpu space
motorola mc68331 26 mc68331ts/d 3.4.4 address strobe as is a timing signal that indicates the validity of an address on the address bus and the validity of many control signals. it is asserted one-half clock after the beginning of a bus cycle. 3.4.5 data bus data bus signals data[15:0] make up a bidirectional, non-multiplexed parallel bus that transfers data to or from the mcu. a read or write operation can transfer 8 or 16 bits of data in one bus cycle. during a read cycle, the data is latched by the mcu on the last falling edge of the clock for that bus cycle. for a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. the mcu places the data on the data bus one-half clock cycle after as is asserted in a write cycle. 3.4.6 data strobe data strobe (ds ) is a timing signal. for a read cycle, the mcu asserts ds to signal an external device to place data on the bus. ds is asserted at the same time as as during a read cycle. for a write cycle, ds signals an external device that data on the bus is valid. the mcu asserts ds one full clock cycle after the assertion of as during a write cycle. 3.4.7 bus cycle termination signals during bus cycles, external devices assert the data transfer and size acknowledge signals (dsack1 and dsack0 ). during a read cycle, the signals tell the mcu to terminate the bus cycle and to latch data. during a write cycle, the signals indicate that an external device has successfully stored data and that the cycle can end. these signals also indicate to the mcu the size of the port for the bus cycle just com- pleted. (refer to 3.4.9 dynamic bus sizing.) the bus error (berr ) signal is also a bus cycle termination indicator and can be used in the absence of dsack1 and dsack0 to indicate a bus error condition. it can also be asserted in conjunction with these signals, provided it meets the appropriate timing requirements. the internal bus monitor can be used to generate the berr signal for internal and internal-to-external transfers. when berr and halt are asserted simultaneously, the cpu takes a bus error exception. autovector signal (avec ) can terminate external irq pin interrupt acknowledge cycles. avec indicates that the mcu will internally generate a vector number to locate an interrupt handler routine. if it is con- tinuously asserted, autovectors will be generated for all external interrupt requests. avec is ignored during all other bus cycles. 3.4.8 data transfer mechanism the mcu architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge inputs (dsack1 and dsack0 ). 3.4.9 dynamic bus sizing the mcu dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8- and 16-bit ports. during an operand transfer cycle, the slave device sig- nals its port size and indicates completion of the bus cycle to the mcu through the use of the dsack0 and dsack1 inputs, as shown in the following table. table 10 effect of dsack signals dsack1 dsack0 result 1 1 insert wait states in current bus cycle 1 0 complete cycle ?ata bus port size is 8 bits 0 1 complete cycle ?ata bus port size is 16 bits 0 0 reserved
mc68331 motorola mc68331ts/d 27 for example, if the mcu is executing an instruction that reads a long-word operand from a 16-bit port, the mcu latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits. the operation for an 8-bit port is similar, but requires four read cycles. the addressed device uses the dsack0 and dsack1 signals to indicate the port width. for instance, a 16-bit device always returns dsack0 = 1 and dsack1 = 0 for a 16-bit port, regardless of whether the bus cycle is a byte or word operation. dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. a 16-bit port must reside on data bus bits [15:0] and an 8-bit port must reside on data bus bits [15:8]. this minimizes the number of bus cycles needed to transfer data and ensures that the mcu transfers valid data. the mcu always attempts to transfer the maximum amount of data on all bus cycles. for a word oper- ation, it is assumed that the port is 16 bits wide when the bus cycle begins. operand bytes are desig- nated as shown in the following figure. op0 is the most significant byte of a long-word operand, and op3 is the least significant byte. the two bytes of a word-length operand are op0 (most significant) and op1. the single byte of a byte-length operand is op0. figure 8 operand byte order 3.4.10 operand alignment the data multiplexer establishes the necessary connections for different combinations of address and data sizes. the multiplexer takes the two bytes of the 16-bit bus and routes them to their required po- sitions. positioning of bytes is determined by the size and address outputs. siz1 and siz0 indicate the remaining number of bytes to be transferred during the current bus cycle. the number of bytes trans- ferred is equal to or less than the size indicated by siz1 and siz0, depending on port width. addr0 also affects the operation of the data multiplexer. during an operand transfer, addr[23:1] in- dicate the word base address of the portion of the operand to be accessed, and addr0 indicates the byte offset from the base. 3.4.11 misaligned operands cpu32 processor architecture uses a basic operand size of 16 bits. an operand is misaligned when it overlaps a word boundary. this is determined by the value of addr0. when addr0 = 0 (an even ad- dress), the address is on a word and byte boundary. when addr0 = 1 (an odd address), the address is on a byte boundary only. a byte operand is aligned at any address; a word or long-word operand is misaligned at an odd address. mc68300 devices do not support misaligned operand transfers. the largest amount of data that can be transferred by a single bus cycle is an aligned word. if the mcu transfers a long-word operand via a 16-bit port, the most significant operand word is transferred on the first bus cycle and the least significant operand word on a following bus cycle. 3.4.12 operand transfer cases the following table summarizes how operands are aligned for various types of transfers. opn entries are portions of a requested operand that are read or written during a bus cycle and are defined by siz1, siz0, and addr0 for that bus cycle. operand byte order 31 24 23 16 15 8 7 0 long word op0 op1 op2 op3 three byte op0 op1 op2 word op0 op1 byte op0
motorola mc68331 28 mc68331ts/d notes: 1. operands in parentheses are ignored by the cpu32 during read cycles. 2. three-byte transfer cases occur only as a result of a long word to byte transfer. 3. the cpu32 does not support misaligned word or long-word transfers. 3.5 chip selects typical microcontrollers require additional hardware to provide external chip-select signals. twelve in- dependently programmable chip selects provide fast two-cycle access to external memory or peripher- als. address block sizes of 2 kbytes to 1 mbyte can be selected. chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobes, or interrupt acknowledge signals. logic can also generate dsack signals internally. a single dsack generator is shared by all circuits. multiple chip selects assigned to the same address and con- trol must have the same number of wait states. chip selects can also be synchronized with the eclk signal available on addr23. when a memory access occurs, chip-select logic compares address space type, address, type of ac- cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in chip-select registers. if all parameters match, the appropriate chip-select signal is asserted. select sig- nals are active low. refer to the following block diagram of a single chip-select circuit. table 11 operand alignment transfer case siz1 siz0 addr0 dsack1 dsack0 data [15:8] data [7:0] byte to 8-bit port (even/odd) 0 1 x 1 0 op0 (op0) byte to 16-bit port (even) 0 1 0 0 x op0 (op0) byte to 16-bit port (odd) 0 1 1 0 x (op0) op0 word to 8-bit port (aligned) 1 0 0 1 0 op0 (op1) word to 8-bit port (misaligned) 3 1 0 1 1 0 op0 (op0) word to 16-bit port (aligned) 1 0 0 0 x op0 op1 word to 16-bit port (misaligned) 3 1 0 1 0 x (op0) op0 3 byte to 8-bit port (aligned) 2 1 1 0 1 0 op0 (op1) 3 byte to 8-bit port (misaligned) 2, 3 1 1 1 1 0 op0 (op0) 3 byte to 16-bit port (aligned) 2 1 1 0 0 x op0 op1 3 byte to 16-bit port (misaligned) 2, 3 1 1 1 0 x (op0) op0 long word to 8-bit port (aligned) 0 0 0 1 0 op0 (op1) long word to 8-bit port (misaligned) 3 1 0 1 1 0 op0 (op0) long word to 16-bit port (aligned) 0 0 0 0 x op0 op1 long word to 16-bit port (misaligned) 3 1 0 1 0 x (op0) op0
mc68331 motorola mc68331ts/d 29 figure 9 chip-select circuit block diagram the following table lists allocation of chip-selects and discrete outputs on the pins of the mcu. 3.5.1 chip-select registers pin assignment registers cspar0 and cspar1 determine functions of chip-select pins. these regis- ters also determine port size (8- or 16-bit) for dynamic bus allocation. a pin data register (portc) latches discrete output data. blocks of addresses are assigned to each chip-select function. block sizes of 2 kbytes to 1 mbyte can be selected by writing values to the appropriate base address register (csbar). address blocks for separate chip-select functions can overlap. chip-select option registers (csorbt and csor[10:0]) determine timing of and conditions for asser- tion of chip-select signals. eight parameters, including operating mode, access size, synchronization, and wait state insertion can be specified. initialization code often resides in a peripheral memory device controlled by the chip-select circuits. a set of special chip-select functions and registers (csorbt, csbarbt) is provided to support bootstrap operation. pin chip select discrete outputs csboot csboot br cs0 bg cs1 bgack cs2 fc0 cs3 pc0 fc1 cs4 pc1 fc2 cs5 pc2 addr19 cs6 pc3 addr20 cs7 pc4 addr21 cs8 pc5 addr22 cs9 pc6 addr23 cs10 eclk chip sel block avec generator dsack generator pin assignment register pin data register base address register timing and control address comparator option compare option register avec dsack pin bus control internal signals address
motorola mc68331 30 mc68331ts/d 3.5.2 pin assignment registers the pin assignment registers (cspar0 and cspar1) contain pairs of bits that determine the function of chip-select pins. the pin assignment encodings used in these registers are shown below. cspar0 contains seven 2-bit fields that determine the functions of corresponding chip-select pins. cspar0[15:14] are not used. these bits always read zero; writes have no effect. cspar0 bit 1 always reads one; writes to cspar0 bit 1 have no effect. cspar1 contains five 2-bit fields that determine the functions of corresponding chip-select pins. cspar1[15:10] are not used. these bits always read zero; writes have no effect. table 12 pin assignment encodings bit field description 00 discrete output 01 alternate function 10 chip select (8-bit port) 11 chip select (16-bit port) cspar0 ?hip select pin assignment register 0 $yffa44 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 cspa0[6] cspa0[5] cspa0[4] cspa0[3] cspa0[2] cspa0[1] csboot reset: 0 0 data2 1 data2 1 data2 1 data1 1 data1 1 data1 1 1 data0 table 13 cspar0 pin assignments cspar0 field chip select signal alternate signal discrete output cspa0[6] cs5 fc2 pc2 cspa0[5] cs4 fc1 pc1 cspa0[4] cs3 fc0 pc0 cspa0[3] cs2 bgack cspa0[2] cs1 bg cspa0[1] cs0 br csboot csboot cspar1 ?hip select pin assignment register 1 $yffa46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cspa1[4] cspa1[3] cspa1[2] cspa1[1] cspa1[0] reset: 0 0 0 0 0 0 data7 1 data [7:6] 1 data [7:5] 1 data [7:4] 1 data [7:3] 1 table 14 cspar1 pin assignments cspar0 field chip select signal alternate signal discrete output cspa1[4] cs10 addr23 eclk cspa1[3] cs9 addr22 pc6 cspa1[2] cs8 addr21 pc5 cspa1[1] cs7 addr20 pc4 cspa1[0] cs6 addr19 pc3
mc68331 motorola mc68331ts/d 31 at reset, either the alternate function (01) or chip-select function (11) can be encoded. data pins are driven to logic level one by a weak internal pull-up during reset. encoding is for chip-select function un- less a data line is held low during reset. note that bus loading can overcome the weak pull-up and hold pins low during reset. the following table shows the hierarchical selection method that determines the reset functions of pins controlled by cspar1. a pin programmed as a discrete output drives an external signal to the value specified in the port c pin data register (portc), with the following exceptions: a. no discrete output function is available on pins br , bg , or bgack . b. addr23 provides e-clock output rather than a discrete output signal. when a pin is programmed for discrete output or alternate function, internal chip-select logic still func- tions and can be used to generate dsack or avec internally on an address match. port size is determined when a pin is assigned as a chip select. when a pin is assigned to an 8-bit port, the chip select is asserted at all addresses within the block range. if a pin is assigned to a 16-bit port, the upper/lower byte field of the option register selects the byte with which the chip select is associated. 3.5.3 base address registers a base address is the starting address for the block enabled by a given chip select. block size deter- mines the extent of the block above the base address. each chip select has an associated base register so that an efficient address map can be constructed for each application. if a chip-select base address register is programmed with the same address as a microcontroller module or memory array, an access to that address goes to the module or array and the chip-select signal is not asserted. blksz ?lock size field this field determines the size of the block that must be enabled by the chip select. the following table shows bit encoding for the base address registers block size field. table 15 reset pin function of cs[10:6] data bus pins at reset chip-select/address bus pin function data7 data6 data5 data4 data3 cs10 / addr23 cs9 / addr22 cs8 / addr21 cs7 / addr20 cs6 / addr19 11111 cs10 cs9 cs8 cs7 cs6 1111 0 cs10 cs9 cs8 cs7 addr19 111 0 x cs10 cs9 cs8 addr20 addr19 11 0 x x cs10 cs9 addr21 addr20 addr19 1 0 x x x cs10 addr22 addr21 addr20 addr19 0xxxx addr23 addr22 addr21 addr20 addr19 csbarbt ?chip-select base address register boot rom $yffa48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 addr 23 addr 22 addr 21 addr 20 addr 19 addr 18 addr 17 addr 16 addr 15 addr 14 addr 13 addr 12 addr 11 blksz reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 csbar[10:0] ?hip-select base address registers $yffa4c?yffa74 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 addr 23 addr 22 addr 21 addr 20 addr 19 addr 18 addr 17 addr 16 addr 15 addr 14 addr 13 addr 12 addr 11 blksz reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola mc68331 32 mc68331ts/d addr[23:11] ?ase address field this field sets the starting address of a particular address space. the address compare logic uses only the most significant bits to match an address within a block. the value of the base address must be a multiple of block size. base address register diagrams show how base register bits correspond to ad- dress lines. 3.5.4 option registers the option registers contain eight fields that determine timing of and conditions for assertion of chip- select signals. for a chip-select signal to be asserted, all bits in the base address register must match the corresponding internal upper address lines, and all conditions specified in the option register must be satisfied. these conditions also apply to providing dsack or autovector support. csorbt, the option register for csboot , contains special reset values that support bootstrap opera- tions from peripheral memory devices. the following bit descriptions apply to both csorbt and csor[10:0] option registers. mode ?synchronous/synchronous mode 0 = asynchronous mode selected (chip-select assertion determined by internal or external bus con- trol signals) 1 = synchronous mode selected (chip-select assertion synchronized with eclk signal) in asynchronous mode, the chip select is asserted synchronized with as or ds . the dsack field is not used in synchronous mode because a bus cycle is only performed as a syn- chronous operation. when a match condition occurs on a chip select programmed for synchronous op- eration, the chip select signals the ebi that an eclk cycle is pending. byte ?pper/lower byte option this field is used only when the chip-select 16-bit port option is selected in the pin assignment register. the following table lists upper/lower byte options. block size field block size address lines compared 000 2 k addr[23:11] 001 8 k addr[23:13] 010 16 k addr[23:14] 011 64 k addr[23:16] 100 128 k addr[23:17] 101 256 k addr[23:18] 110 512 k addr[23:19] 111 1 m addr[23:20] csorbt ?hip-select option register boot rom $yffa4a 15 14 13 12 11 10 9 6 5 4 3 1 0 mode byte r/w strb dsack space ipl avec reset: 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 csor[10:0] ?hip-select option registers $yffa4e?yffa76 15 14 13 12 11 10 9 6 5 4 3 1 0 mode byte r/w strb dsack space ipl avec reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
mc68331 motorola mc68331ts/d 33 r/w ?ead/write this field causes a chip select to be asserted only for a read, only for a write, or for both read and write. refer to the following table for options available. strb ?ddress strobe/data strobe 0 = address strobe 1 = data strobe this bit controls the timing for assertion of a chip select in asynchronous mode. selecting address strobe causes chip select to be asserted synchronized with address strobe. selecting data strobe caus- es chip select to be asserted synchronized with data strobe. dsack ?ata and size acknowledge this field specifies the source of dsack in asynchronous mode. it also allows the user to adjust bus timing with internal dsack generation by controlling the number of wait states that are inserted to op- timize bus speed in a particular application. the following table shows the dsack field encoding. the fast termination encoding (1110) is used for two-cycle access to external memory. byte description 00 disable 01 lower byte 10 upper byte 11 both bytes r/w description 00 reserved 01 read only 10 write only 11 read/write dsack description 0000 no wait states 0001 1 wait state 0010 2 wait states 0011 3 wait states 0100 4 wait states 0101 5 wait states 0110 6 wait states 0111 7 wait states 1000 8 wait states 1001 9 wait states 1010 10 wait states 1011 11 wait states 1100 12 wait states 1101 13 wait states 1110 fast termination 1111 external dsack
motorola mc68331 34 mc68331ts/d space ?ddress space use this option field to select an address space for the chip-select logic. the cpu32 normally operates in supervisor or user space, but interrupt acknowledge cycles must take place in cpu space. ipl ?nterrupt priority level if the space field is set for cpu space (00), chip-select logic can be used for interrupt acknowledge. during an interrupt acknowledge cycle, the priority level on address lines addr[3:1] is compared to the value in the ipl field. if the values are the same, a chip select is asserted, provided that other option register conditions are met. the following table shows ipl field encoding. this field only affects the response of chip selects and does not affect interrupt recognition by the cpu. any level means that chip select is asserted regardless of the level of the interrupt acknowledge cycle. avec ?utovector enable 0 = external interrupt vector enabled 1 = autovector enabled this field selects one of two methods of acquiring the interrupt vector during the interrupt acknowledge cycle. it is not usually used in conjunction with a chip-select pin. if the chip select is configured to trigger on an interrupt acknowledge cycle (space = 00) and the avec field is set to one, the chip select automatically generates an avec in response to the interrupt cycle. otherwise, the vector must be supplied by the requesting device. the avec bit must not be used in synchronous mode, as autovector response timing can vary because of eclk synchronization. 3.5.5 port c data register bit values in port c determine the state of chip-select pins used for discrete output. when a pin is as- signed as a discrete output, the value in this register appears at the output. this is a read/write register. bit 7 is not used. writing to this bit has no effect, and it always returns zero when read. space field address space 00 cpu space 01 user space 10 supervisor space 11 supervisor/user space ipl description 000 any level 001 ipl1 010 ipl2 011 ipl3 100 ipl4 101 ipl5 110 ipl6 111 ipl7 portc ?port c data register $yffa41 15 8 7 6 5 4 3 2 1 0 not used 0 pc6 pc5 pc4 pc3 pc2 pc1 pc0 reset: 0 1 1 1 1 1 1 1
mc68331 motorola mc68331ts/d 35 3.6 general-purpose input/output sim pins can be configured as two general-purpose i/o ports, e and f. the following paragraphs de- scribe registers that control the ports. a write to the port e data register is stored in the internal data latch and, if any port e pin is configured as an output, the value stored for that bit is driven on the pin. a read of the port e data register returns the value at the pin only if the pin is configured as a discrete input. otherwise, the value read is the value stored in the register. the port e data register is a single register that can be accessed in two locations. when accessed at $yffa11, the register is referred to as porte0; when accessed at $yffa13, the register is referred to as porte1. the register can be read or written at any time. it is unaffected by reset. the bits in this register control the direction of the pin drivers when the pins are configured as i/o. any bit in this register set to one configures the corresponding pin as an output. any bit in this register cleared to zero configures the corresponding pin as an input. this register can be read or written at any time. the bits in this register control the function of each port e pin. any bit set to one configures the corre- sponding pin as a bus control signal, with the function shown in the following table. any bit cleared to zero defines the corresponding pin to be an i/o pin, controlled by porte and ddre. data bus bit 8 controls the state of this register following reset. if data8 is set to one during reset, the register is set to $ff, which defines all port e pins as bus control signals. if data8 is cleared to zero during reset, this register is set to $00, configuring all port e pins as i/o pins. any bit cleared to zero defines the corresponding pin to be an i/o pin. any bit set to one defines the corresponding pin to be a bus control signal. porte0, porte1 ?ort e data register $yffa11, $yffa13 15 8 7 6 5 4 3 2 1 0 not used pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 reset: u u u u u u u u ddre ?port e data direction register $yffa15 15 8 7 6 5 4 3 2 1 0 not used dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 reset: 0 0 0 0 0 0 0 0 pepar ?port e pin assignment register $yffa17 15 8 7 6 5 4 3 2 1 0 not used pepa7 pepa6 pepa5 pepa4 pepa3 pepa2 pepa1 pepa0 reset: data8 data8 data8 data8 data8 data8 data8 data8 table 16 port e pin assignments pepar bit port e signal bus control signal pepa7 pe7 siz1 pepa6 pe6 siz0 pepa5 pe5 as pepa4 pe4 ds pepa3 pe3 rmc pepa2 pe2 avec pepa1 pe1 dsack1 pepa0 pe0 dsack0
motorola mc68331 36 mc68331ts/d the write to the port f data register is stored in the internal data latch, and if any port f pin is configured as an output, the value stored for that bit is driven onto the pin. a read of the port f data register returns the value at the pin only if the pin is configured as a discrete input. otherwise, the value read is the value stored in the register. the port f data register is a single register that can be accessed in two locations. when accessed at $yffa19, the register is referred to as portf0; when accessed at $yffa1b, the register is referred to as portf1. the register can be read or written at any time. it is unaffected by reset. the bits in this register control the direction of the pin drivers when the pins are configured for i/o. any bit in this register set to one configures the corresponding pin as an output. any bit in this register cleared to zero configures the corresponding pin as an input. the bits in this register control the function of each port f pin. any bit cleared to zero defines the corre- sponding pin to be an i/o pin. any bit set to one defines the corresponding pin to be an interrupt request signal or modclk. the modclk signal has no function after reset. data bus pin 9 controls the state of this register following reset. if data9 is set to one during reset, the register is set to $ff, which defines all port f pins as interrupt request inputs. if data9 is cleared to zero during reset, this register is set to $00, defining all port f pins as i/o pins. portf0, portf1 ?port f data register $yffa19, $yffa1b 15 8 7 6 5 4 3 2 1 0 not used pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset: u u u u u u u u ddrf ?port f data direction register $yffa1d 15 8 7 6 5 4 3 2 1 0 not used ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 reset: 0 0 0 0 0 0 0 0 pfpar ?port f pin assignment register $yffa1f 15 8 7 6 5 4 3 2 1 0 not used pfpa7 pfpa6 pfpa5 pfpa4 pfpa3 pfpa2 pfpa1 pfpa0 reset: data9 data9 data9 data9 data9 data9 data9 data9 table 17 port f pin assignments pfpar field port f signal alternate signal pfpa7 pf7 irq7 pfpa6 pf6 irq6 pfpa5 pf5 irq5 pfpa4 pf4 irq4 pfpa3 pf3 irq3 pfpa2 pf2 irq2 pfpa1 pf1 irq1 pfpa0 pf0 modclk
mc68331 motorola mc68331ts/d 37 3.7 resets reset procedures handle system initialization and recovery from catastrophic failure. the mcu per- forms resets with a combination of hardware and software. the system integration module determines whether a reset is valid, asserts control signals, performs basic system configuration based on hard- ware mode-select inputs, then passes control to the cpu. reset occurs when an active low logic level on the reset pin is clocked into the sim. resets are gated by the clkout signal. asynchronous resets are assumed to be catastrophic. an asynchronous reset can occur on any clock edge. synchronous resets are timed to occur at the end of bus cycles. if there is no clock when reset is asserted, reset does not occur until the clock starts. resets are clocked in order to allow completion of write cycles in progress at the time reset is asserted. reset is the highest-priority cpu32 exception. any processing in progress is aborted by the reset ex- ception, and cannot be restarted. only essential tasks are performed during reset exception processing. other initialization tasks must be accomplished by the exception handler routine. 3.7.1 sim reset mode selection the logic states of certain data bus pins during reset determine sim operating configuration. in addition, the state of the modclk pin determines system clock source and the state of the bkpt pin determines what happens during subsequent breakpoint assertions. the following table is a summary of reset mode selection options. 3.7.2 functions of pins for other modules during reset generally, pins associated with modules other than the sim default to port functions, and input/output ports are set to input state. this is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers. refer to individual module sec- tions in this manual for more information. the following table is a summary of module pin function out of reset. table 18 reset mode selection mode select pin default function (pin left high) alternate function (pin pulled low) data0 csboot 16-bit csboot 8-bit data1 cs0 cs1 cs2 br bg bgack data2 cs3 cs4 cs5 fc0 fc1 fc2 data3 data4 data5 data6 data7 cs6 cs[7:6] cs[8:6] cs[9:6] cs[10:6] addr19 addr[20:19] addr[21:19] addr[22:19] addr[23:19] data8 dsack0 , dsack1 , avec , ds , as , siz[1:0] porte data9 irq[7:1] modclk portf data11 test mode disabled test mode enabled modclk vco = system clock extal = system clock bkpt background mode disabled background mode enabled
motorola mc68331 38 mc68331ts/d 3.7.3 reset timing the reset input must be asserted for a specified minimum period in order for reset to occur. external reset assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor time-out period) in order to protect write cycles from being aborted by reset. while reset is asserted, sim pins are either in a disabled high-impedance state or are driven to their inactive states. when an external device asserts reset for the proper period, reset control logic clocks the signal into an internal latch. the control logic drives the reset pin low for an additional 512 clkout cycles after it detects that the reset signal is no longer being externally driven, to guarantee this length of reset to the entire system. if an internal source asserts a reset signal, the reset control logic asserts reset for a minimum of 512 cycles. if the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert reset until the internal reset signal is negated. after 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cy- cles. at the end of this 10-cycle period, the reset input is tested. when the input is at logic level one, reset exception processing begins. if, however, the reset input is at logic level zero, the reset control logic drives the pin low for another 512 cycles. at the end of this period, the pin again goes to high- impedance state for 10 cycles, then it is tested again. the process repeats until reset is released. 3.7.4 power-on reset when the sim clock synthesizer is used to generate the system clock, power-on reset involves special circumstances related to application of system and clock synthesizer power. regardless of clock source, voltage must be applied to clock synthesizer power input pin v ddsyn in order for the mcu to operate. the following discussion assumes that v ddsyn is applied before and during reset. this mini- mizes crystal start-up time. when v ddsyn is applied at power-on, start-up time is affected by specific crystal parameters and by oscillator circuit design. v dd ramp-up time also affects pin state during reset. during power-on reset, an internal circuit in the sim drives the internal (imb) and external reset lines. the circuit releases the internal reset line as v dd ramps up to the minimum specified value, and sim pins are initialized. when v dd reaches the specified minimum value, the clock synthesizer vco begins operation. clock frequency ramps up to the specified limp mode frequency. the external reset line remains asserted until the clock synthesizer pll locks and 512 clkout cycles elapse. table 19 module pin functions module pin mnemonic function cpu32 dsi/ifetch dsi/ifetch dso/ipipe dso/ipipe bkpt /dsclk bkpt /dsclk gpt pgp7/ic4/oc5 discrete input pgp[6:3]/oc[4:1] discrete input pgp[2:0]/ic[3:1] discrete input pai discrete input pclk discrete input pwma, pwmb discrete output qsm pqs7/txd discrete input pqs[6:4]/pcs[3:1] discrete input pqs3/pcs0/ss discrete input pqs2/sck discrete input pqs1/mosi discrete input pqs0/miso discrete input rxd rxd
mc68331 motorola mc68331ts/d 39 the sim clock synthesizer provides clock signals to the other mcu modules. after the clock is running and the internal reset signal is asserted for four clock cycles, these modules reset. v dd ramp time and vco frequency ramp time determine how long these four cycles take. worst case is approximately 15 milliseconds. during this period, module port pins may be in an indeterminate state. while input-only pins can be put in a known state by means of external pull-up resistors, external logic on input/output or output-only pins must condition the lines during this time. active drivers require high-impedance buff- ers or isolation resistors to prevent conflict. 3.7.5 use of three state control pin asserting the three-state control (tsc) input causes the mcu to put all output drivers in an inactive, high-impedance state. the signal must remain asserted for 10 clock cycles in order for drivers to change state. there are certain constraints on use of tsc during power-on reset: when the internal clock synthesizer is used (modclk held high during reset), synthesizer ramp- up time affects how long the 10 cycles take. worst case is approximately 20 milliseconds from tsc assertion. when an external clock signal is applied (modclk held low during reset), pins go to high-imped- ance state as soon after tsc assertion as 10 clock pulses have been applied to the extal pin. when tsc assertion takes effect, internal signals are forced to values that can cause inadvertent mode selection. once the output drivers change state, the mcu must be powered down and re- started before normal operation can resume. 3.8 interrupts interrupt recognition and servicing involve complex interaction between the central processing unit, the system integration module, and a device or module requesting interrupt service. the cpu32 provides for eight levels of interrupt priority (0?), seven automatic interrupt vectors and 200 assignable interrupt vector. all interrupts with priorities less than 7 can be masked by the interrupt priority (ip) field in the status register. the cpu32 handles interrupts as a type of asynchronous excep- tion. interrupt recognition is based on the states of interrupt request signals irq[7:1] and the ip mask value. each of the signals corresponds to an interrupt priority. irq1 has the lowest priority, and irq7 has the highest priority. the ip field consists of three bits. binary values %000 to %111 provide eight priority masks. masks pre- vent an interrupt request of a priority less than or equal to the mask value (except for irq7 ) from being recognized and processed. when ip contains %000, no interrupt is masked. during exception process- ing, the ip field is set to the priority of the interrupt being serviced. interrupt request signals can be asserted by external devices or by microcontroller modules. request lines are connected internally by means of a wired nor ?simultaneous requests of differing priority can be made. internal assertion of an interrupt request signal does not affect the logic state of the cor- responding mcu pin. external interrupt requests are routed to the cpu via the external bus interface and sim interrupt control logic. the cpu treats external interrupt requests as though they come from the sim. external irq[6:1] are active-low level-sensitive inputs. external irq7 is an active-low transition-sensi- tive input. irq7 requires both an edge and a voltage level for validity. irq[6:1] are maskable. irq7 is nonmaskable. the irq7 input is transition-sensitive in order to prevent redundant servicing and stack overflow. a nonmaskable interrupt is generated each time irq7 is as- serted, and each time the priority mask changes from %111 to a lower number while irq7 is asserted.
motorola mc68331 40 mc68331ts/d interrupt requests are sampled on consecutive falling edges of the system clock. interrupt request input circuitry has hysteresis. to be valid, a request signal must be asserted for at least two consecutive clock periods. valid requests do not cause immediate exception processing, but are left pending. pending re- quests are processed at instruction boundaries or when exception processing of higher-priority excep- tions is complete. the cpu32 does not latch the priority of a pending interrupt request. if an interrupt source of higher priority makes a service request while a lower priority request is pending, the higher priority request is serviced. if an interrupt request of equal or lower priority than the current ip mask value is made, the cpu does not recognize the occurrence of the request in any way. 3.8.1 interrupt acknowledge and arbitration interrupt acknowledge bus cycles are generated during exception processing. when the cpu detects one or more interrupt requests of a priority higher than the interrupt priority mask value, it performs a cpu space read from address $fffff : [ip] : 1. the cpu space read cycle performs two functions: it places a mask value corresponding to the highest priority interrupt request on the address bus, and it acquires an exception vector number from the inter- rupt source. the mask value also serves two purposes: it is latched into the ccr ip field in order to mask lower-priority interrupts during exception processing, and it is decoded by modules that have re- quested interrupt service to determine whether the current interrupt acknowledge cycle pertains to them. modules that have requested interrupt service decode the ip value placed on the address bus at the beginning of the interrupt acknowledge cycle, and if their requests are at the specified ip level, respond to the cycle. arbitration between simultaneous requests of the same priority is performed by means of serial contention between module interrupt arbitration (iarb) field bit values. each module that can make an interrupt service request, including the sim, has an iarb field in its con- figuration register. an iarb field can be assigned a value from %0001 (lowest priority) to %1111 (high- est priority). a value of %0000 in an iarb field causes the cpu to process a spurious interrupt exception when an interrupt from that module is recognized. because the ebi manages external interrupt requests, the sim iarb value is used for arbitration be- tween internal and external interrupt requests. the reset value of iarb for the sim is %1111, and the reset iarb value for all other modules is %0000. initialization software must assign different iarb val- ues in order to implement an arbitration scheme. each module must have a unique iarb value. when two or more iarb fields have the same nonzero value, the cpu interprets multiple vector numbers simultaneously, with unpredictable consequences. arbitration must always take place, even when a single source requests service. this point is important for two reasons: the cpu interrupt acknowledge cycle is not driven on the external bus unless the sim wins contention, and failure to contend causes an interrupt acknowledge bus cycle to be terminated by a bus error, which causes a spurious interrupt exception to be taken. when arbitration is complete, the dominant module must place an interrupt vector number on the data bus and terminate the bus cycle. in the case of an external interrupt request, because the interrupt ac- knowledge cycle is transferred to the external bus, an external device must decode the mask value and respond with a vector number, then generate bus cycle termination signals. if the device does not re- spond in time, a spurious interrupt exception is taken. the periodic interrupt timer (pit) in the sim can generate internal interrupt requests of specific priority at predetermined intervals. by hardware convention, pit interrupts are serviced before external inter- rupt service requests of the same priority. refer to 3.2.7 periodic interrupt timer for more information.
mc68331 motorola mc68331ts/d 41 3.8.2 interrupt processing summary a summary of the interrupt processing sequence follows. when the sequence begins, a valid interrupt service request has been detected and is pending. a. the cpu finishes higher priority exception processing or reaches an instruction boundary. b. processor state is stacked. the contents of the status register and program counter are saved. c. the interrupt acknowledge cycle begins: 1. fc[2:0] are driven to %111 (cpu space) encoding. 2. the address bus is driven as follows. addr[23:20] = %1111; addr[19:16] = %1111, which indicates that the cycle is an interrupt acknowledge cpu space cycle; addr[15:4] = %111111111111; addr[3:1] = the level of the interrupt request being acknowledged; and addr0 = %1. 3. request priority level is latched into the ip field in the status register from the address bus. d. modules or external peripherals that have requested interrupt service decode the request level in addr[3:1]. if the request level of at least one interrupting module or device is the same as the value in addr[3:1], interrupt arbitration contention takes place. when there is no conten- tion, the spurious interrupt monitor asserts berr , and a spurious interrupt exception is pro- cessed. e. after arbitration, the interrupt acknowledge cycle can be completed in one of three ways: 1. the dominant interrupt source supplies a vector number and dsack signals appropriate to the access. the cpu32 acquires the vector number. 2. the avec signal is asserted (the signal can be asserted by the dominant interrupt source or the pin can be tied low), and the cpu32 generates an autovector number corresponding to interrupt priority. 3. the bus monitor asserts berr and the cpu32 generates the spurious interrupt vector number. f. the vector number is converted to a vector address. g. the content of the vector address is loaded into the pc, and the processor transfers control to the exception handler routine. 3.9 factory test block the test submodule supports scan-based testing of the various mcu modules. it is integrated into the sim to support production testing. test submodule registers are intended for motorola use. register names and addresses are provided to indicate that these addresses are occupied. simtr ?system integration module test register $yffa02 simtre ?system integration module test register (e clock) $yffa08 tstmsra ?master shift register a $yffa30 tstmsrb ?master shift register b $yffa32 tstsc ?test module shift count $yffa34 tstrc ?test module repetition count $yffa36 creg ?test module control register $yffa38 dreg ?test module distributed register $yffa3a
motorola mc68331 42 mc68331ts/d
mc68331 motorola mc68331ts/d 43 4 central processor unit based on the powerful mc68020, the cpu32 processing module provides enhanced system perfor- mance and also uses the extensive software base for the motorola m68000 family. 4.1 overview the cpu32 is fully object code compatible with the m68000 family, which excels at processing calcu- lation-intensive algorithms and supporting high-level languages. the cpu32 supports all of the mc68010 and most of the mc68020 enhancements, such as virtual memory support, loop mode oper- ation, instruction pipeline, and 32-bit mathematical operations. powerful addressing modes provide compatibility with existing software programs and increase the efficiency of high-level language compil- ers. special instructions, such as table lookup and interpolate and low-power stop, support the specific requirements of controller applications. also included is the background debugging mode, an alternate operating mode that suspends normal operation and allows the cpu to accept debugging commands from the development system. ease of programming is an important consideration in using a microcontroller. the cpu32 instruction set is optimized for high performance. the eight 32-bit general-purpose data registers readily support 8-bit (byte), 16-bit (word), and 32-bit (long word) operations. ease of program checking and diagnosis is further enhanced by trace and trap capabilities at the instruction level. use of high-level languages is increasing as controller applications become more complex and control programs become larger. high-level languages aid rapid development of software, with less error, and are readily portable. the cpu32 instruction set supports high-level languages. 4.2 programming model the cpu32 has sixteen 32-bit general registers, a 32-bit program counter, one 32-bit supervisor stack pointer, a 16-bit status register, two alternate function code registers, and a 32-bit vector base register. the programming model of the cpu32 consists of a user model and supervisor model, corresponding to the user and supervisor privilege levels. some instructions available at the supervisor level are not available at the user level, allowing the supervisor to protect system resources from uncontrolled ac- cess. bit s in the status register determines the privilege level. the user programming model remains unchanged from previous m68000 family microprocessors. ap- plication software written to run at the nonprivileged user level migrates without modification to the cpu32 from any m68000 platform. the move from sr instruction, however, is privileged in the cpu32. it is not privileged in the m68000.
motorola mc68331 44 mc68331ts/d 31 16 15 8 7 0 d0 d1 d2 d3 data registers d4 d5 d6 d7 31 16 15 0 a0 a1 a2 a3 address registers a4 a5 a6 31 16 15 0 a7 (usp) user stack pointer 31 0 pc program counter 70 ccr condition code register figure 10 user programming model 31 16 15 0 a7' (ssp) supervisor stack pointer 15 8 7 0 (ccr) sr status register 31 0 vbr vector base register 20 sfc alternate function dfc code registers figure 11 supervisor programming model supplement
mc68331 motorola mc68331ts/d 45 4.3 status register the status register contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. the lower byte containing the condition codes is the only portion of the register available at the user privilege level; it is referenced as the con- dition code register (ccr) in user programs. at the supervisor privilege level, software can access the full status register, including the interrupt priority mask and additional control bits. system byte t[1:0] ?race enable s ?upervisor/user state bits [12:11] ?nimplemented ip[2:0] ?nterrupt priority mask user byte (condition code register) bits [7:5] ?nimplemented x ?xtend n ?egative z ?ero v ?verflow c ?arry 4.4 data types six basic data types are supported: ? bits ? packed binary coded decimal digits ? byte integers (8 bits) ? word integers (16 bits) ? long-word integers (32 bits) ? quad-word integers (64 bits) 4.5 addressing modes addressing in the cpu32 is register-oriented. most instructions allow the results of the specified oper- ation to be placed either in a register or directly in memory. this flexibility eliminates the need for extra instructions to store register contents in memory. the cpu32 supports seven basic addressing modes: ? register direct ? register indirect ? register indirect with index ? program counter indirect with displacement ? program counter indirect with index ? absolute ? immediate included in the register indirect addressing modes are the capabilities to post-increment, predecrement, and offset. the program counter relative mode also has index and offset capabilities. in addition to these addressing modes, many instructions implicitly specify the use of the status register, stack point- er, or program counter. sr ?tatus register 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 t1 t0 s 0 0 ip 0 0 0 x n z v c reset: 0 0 1 0 0 1 1 1 0 0 0 u u u u u
motorola mc68331 46 mc68331ts/d 4.6 instruction set summary table 20 instruction set summary instruction syntax operand size operation abcd dn, dn - (an), - (an) 8 8 source 10 + destination 10 + x t destination add dn, , dn 8, 16, 32 8, 16, 32 source + destination t destination adda , an 16, 32 source + destination t destination addi #, 8, 16, 32 immediate data + destination t destination addq # , 8, 16, 32 immediate data + destination t destination addx dn, dn - (an), - (an) 8, 16, 32 8, 16, 32 source + destination + x t destination and , dn dn, 8, 16, 32 8, 16, 32 source destination t destination andi # , 8, 16, 32 data destination t destination andi to ccr # , ccr 8 source ccr t ccr andi to sr1 1 # , sr 16 source sr t sr asl dn, dn # , dn 8, 16, 32 8, 16, 32 16 asr dn, dn # , dn 8, 16, 32 8, 16, 32 16 bcc label 8, 16, 32 if condition true, then pc + d t pc bchg dn, # , 8, 32 8, 32 bclr dn, # , 8, 32 8, 32 0 t bit of destination bgnd none none if background mode enabled, then enter background mode, else format/vector t - (ssp); pc t - (ssp); sr t - (ssp); (vector) t pc bkpt # none if breakpoint cycle acknowledged, then execute returned operation word, else trap as illegal instruction bra label 8, 16, 32 pc + d t pc bset dn, # , 8, 32 8, 32 1 t bit of destination bsr label 8, 16, 32 sp - 4 t sp; pc t (sp); pc + d t pc btst dn, # , 8, 32 8, 32 chk , dn 16, 32 if dn < 0 or dn > (ea), then chk exception chk2 , rn 8, 16, 32 if rn < lower bound or rn > upper bound, then chk exception clr 8, 16, 32 0 t destination cmp , dn 8, 16, 32 (destination - source), ccr shows results cmpa , an 16, 32 (destination - source), ccr shows results cmpi # , 8, 16, 32 (destination - data), ccr shows results x/c 0 x/c bit number ? of destination ) z bit of destinati o tt bit number ? of destination () z bit number ? of destination () z; t bit number ? of destination () z t
mc68331 motorola mc68331ts/d 47 cmpm (an) + , (an) + 8, 16, 32 (destination - source), ccr shows results cmp2 , rn 8, 16, 32 lower bound rn upper bound, ccr shows result dbcc dn, label 16 if condition false, then dn - 1 t pc; if dn 1 ( - 1), then pc + d t pc divs/divu , dn 32/16 t 16 : 16 destination / source t destination (signed or unsigned) divsl/divul , dr : dq , dq , dr : dq 64/32 t 32 : 32 32/32 t 32 32/32 t 32 : 32 destination / source t destination (signed or unsigned) eor dn, 8, 16, 32 source ? destination t destination eori # , 8, 16, 32 data ? destination t destination eori to ccr # , ccr 8 source ? ccr t ccr eori to sr 1 # , sr 16 source ? sr t sr exg rn, rn 32 rn t rn ext dn dn 8 t 16 16 t 32 sign extended destination t destination extb dn 8 t 32 sign extended destination t destination illegal none none ssp - 2 t ssp; vector offset t (ssp); ssp - 4 t ssp; pc t (ssp); ssp - 2 t ssp; sr t (ssp); illegal instruction vector address t pc jmp none destination t pc jsr none sp - 4 t sp; pc t (sp); destination t pc lea , an 32 t an link an, # d 16, 32 sp - 4 t sp, an t (sp); sp t an, sp + d t sp lpstop 1 # 16 data t sr; interrupt mask t ebi; stop lsl dn, dn # , dn 8, 16, 32 8, 16, 32 16 lsr dn, dn #, dn 8, 16, 32 8, 16, 32 16 move , 8, 16, 32 source t destination movea , an 16, 32 t 32 source t destination movea 1 usp, an an, usp 32 32 usp t an an t usp move from ccr ccr, 16 ccr t destination move to ccr , ccr 16 source t ccr move from sr 1 sr, 16 sr t destination move to sr 1 , sr 16 source t sr move usp 1 usp, an an, usp 32 32 usp t an an t usp movec 1 rc, rn rn, rc 32 32 rc t rn rn t rc movem list, , list 16, 32 16, 32 t 32 listed registers t destination source t listed registers table 20 instruction set summary (continued) instruction syntax operand size operation x/c 0 x/c 0
motorola mc68331 48 mc68331ts/d movep dn, (d16, an) (d16, an), dn 16, 32 dn [31 : 24] t (an + d); dn [23 : 16] t (an + d + 2); dn [15 : 8] t (an + d + 4); dn [7 : 0] t (an + d + 6) (an + d) t dn [31 : 24]; (an + d + 2) t dn [23 : 16]; (an + d + 4) t dn [15 : 8]; (an + d + 6) t dn [7 : 0] moveq #, dn 8 t 32 immediate data t destination moves 1 rn, , rn 8, 16, 32 rn t destination using dfc source using sfc t rn muls/mulu , dn , dl , dh : dl 16 * 16 t 32 32 * 32 t 32 32 * 32 t 64 source * destination t destination (signed or unsigned) nbcd 8 8 0 - destination 10 - x t destination neg 8, 16, 32 0 - destination t destination negx 8, 16, 32 0 - destination - x t destination nop none none pc + 2 t pc not 8, 16, 32 destination t destination or , dn dn, 8, 16, 32 8, 16, 32 source + destination t destination ori #, 8, 16, 32 data + destination t destination ori to ccr #, ccr 16 source + ccr t sr ori to sr 1 #, sr 16 source ; sr t sr pea 32 sp - 4 t sp; t sp reset 1 none none assert reset line rol dn, dn #, dn 8, 16, 32 8, 16, 32 16 ror dn, dn #, dn 8, 16, 32 8, 16, 32 16 roxl dn, dn #, dn 8, 16, 32 8, 16, 32 16 roxr dn, dn #, dn 8, 16, 32 8, 16, 32 16 rtd #d 16 (sp) t pc; sp + 4 + d t sp rte 1 none none (sp) t sr; sp + 2 t sp; (sp) t pc; sp + 4 t sp; restore stack according to format rtr none none (sp) t ccr; sp + 2 t sp; (sp) t pc; sp + 4 t sp rts none none (sp) t pc; sp + 4 t sp sbcd dn, dn - (an), - (an) 8 8 destination10 - source10 - x t destination scc 8 if condition true, then destination bits are set to 1; else, destination bits are cleared to 0 stop 1 # 16 data t sr; stop table 20 instruction set summary (continued) instruction syntax operand size operation c c c x c x
mc68331 motorola mc68331ts/d 49 1. privileged instruction. sub , dn dn, 8, 16, 32 destination - source t destination suba , an 16, 32 destination - source t destination subi #, 8, 16, 32 destination - data t destination subq #, 8, 16, 32 destination - data t destination subx dn, dn - (an), - (an) 8, 16, 32 8, 16, 32 destination - source - x t destination swap dn 16 tas 8 destination tested condition codes bit 7 of destination tbls/tblu , dn dym : dyn, dn 8, 16, 32 dyn - dym t temp (temp * dn [7 : 0]) t temp (dym * 256) + temp t dn tblsn/tblun , dn dym : dyn, dn 8, 16, 32 dyn - dym t temp (temp * dn [7 : 0]) / 256 t temp dym + temp t dn trap # none ssp - 2 t ssp; format/vector offset t (ssp); ssp - 4 t ssp; pc t (ssp); sr t (ssp); vector address t pc trapcc none # none 16, 32 if cc true, then trap exception trapv none none if v set, then overflow trap exception tst 8, 16, 32 source - 0, to set condition codes unlk an 32 an t sp; (sp) t an, sp + 4 t sp table 20 instruction set summary (continued) instruction syntax operand size operation msw lsw
motorola mc68331 50 mc68331ts/d 4.7 background debugging mode the background debugger on the cpu32 is implemented in cpu microcode. the background debug- ging commands are summarized below. table 21 background debugging mode command mnemonic description read d/a register rdreg/rareg read the selected address or data register and return the results through the serial interface. write d/a register wdreg/wareg the data operand is written to the specified address or data register. read system register rsreg the specified system control register is read. all registers that can be read in supervisor mode can be read in background mode. write system register wsreg the operand data is written into the specified system control register. read memory location read read the sized data at the memory location specified by the long-word address. the source function code register (sfc) determines the address space accessed. write memory location write write the operand data to the memory location specified by the long-word address. the destination function code (dfc) register determines the address space accessed. dump memory block dump used in conjunction with the read command to dump large blocks of memory. an initial read is executed to set up the starting address of the block and retrieve the first result. subsequent operands are retrieved with the dump command. fill memory block fill used in conjunction with the write command to fill large blocks of memory. initially, a write is executed to set up the starting address of the block and supply the first operand. the fill command writes subsequent operands. resume execution go the pipe is flushed and refilled before resuming instruction execution at the current pc. patch user code call current program counter is stacked at the location of the current stack pointer. instruction execution begins at user patch code. reset peripherals rst asserts reset for 512 clock cycles. the cpu is not reset by this command. synonymous with the cpu reset instruction. no operation nop nop performs no operation and can be used as a null command.
mc68331 motorola mc68331ts/d 51 5 queued serial module the qsm contains two serial interfaces, the queued serial peripheral interface (qspi) and the serial communication interface (sci). figure 12 qsm block diagram 5.1 overview the qspi provides easy peripheral expansion or interprocessor communication through a full-duplex, synchronous, three-line bus: data in, data out, and a serial clock. four programmable peripheral chip- select pins provide addressability for up to 16 peripheral devices. a self-contained ram queue allows up to 16 serial transfers of 8 to 16 bits each, or transmission of a 256-bit data stream without cpu in- tervention. a special wraparound mode supports continuous sampling of a serial peripheral, with auto- matic qspi ram updating, which makes the interface to a/d converters more efficient. the sci provides a standard nonreturn to zero (nrz) mark/space format. it operates in either full- or half-duplex mode. there are separate transmitter and receiver enable bits and dual data buffers. a modulus-type baud rate generator provides rates from 64 to 524 kbaud with a 16.78-mhz system clock, or 110 to 655 kbaud with a 20.97 mhz system clock. word length of either 8 or 9 bits is software select- able. optional parity generation and detection provide either even or odd parity check capability. ad- vanced error detection circuitry catches glitches of up to 1/16 of a bit time in duration. wakeup functions allow the cpu to run uninterrupted until meaningful data is available. an address map of the qsm is shown below. the ?ccess?column indicates which registers are acces- sible only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege level, according to the value of the supv bit in the qsmcr. qspi interface logic sci miso/pqs0 mosi/pqs1 sck/pqs2 pcs0/ss /pqs3 pcs1/pqs4 pcs2/pqs5 pcs3/pqs6 txd/pqs7 rxd port qs qsm block imb
motorola mc68331 52 mc68331ts/d y = m111, where m is the logic state of the module mapping (mm) bit in the simcr 5.2 pin function the following table is a summary of the functions of the qsm pins when they are not configured for gen- eral-purpose i/o. the qsm data direction register (ddrqs) designates each pin except rxd as an in- put or output. table 22 qsm address map access address 15 8 7 0 s $yffc00 qsm module configuration (qsmcr) s $yffc02 qsm test (qtest) s $yffc04 qsm interrupt level (qilr) qsm interrupt vector (qivr) s/u $yffc06 not used s/u $yffc08 sci control 0 (sccr0) s/u $yffc0a sci control 1 (sccr1) s/u $yffc0c sci status (scsr) s/u $yffc0e sci data (scdr) s/u $yffc10 not used s/u $yffc12 not used s/u $yffc14 not used pqs data (portqs) s/u $yffc16 pqs pin assignment (pqspar) pqs data direction (ddrqs) s/u $yffc18 spi control 0 (spcr0) s/u $yffc1a spi control 1 (spcr1) s/u $yffc1c spi control 2 (spcr2) s/u $yffc1e spi control 3 (spcr3) spi status (spsr) s/u $yffc20 $yffcff not used s/u $yffd00 $yffd1f receive ram (rr[0:f]) s/u $yffd20 $yffd3f transmit ram (tr[0:f]) s/u $yffd40 $yffd4f command ram (cr[0:f]) pin mode pin function miso master serial data input to qspi qspi pins slave serial data output from qspi mosi master serial data output from qspi slave serial data input to qspi sck master clock output from qspi slave clock input to qspi pcs0/ss master input: assertion causes mode fault output: selects peripherals slave input: selects the qspi pcs[3:1] master output: selects peripherals slave none sci pins txd transmit serial data output from sci rxd receive serial data input to sci
mc68331 motorola mc68331ts/d 53 5.3 qsm registers qsm registers are divided into four categories: qsm global registers, qsm pin control registers, qspi submodule registers, and sci submodule registers. the qspi and sci registers are defined in separate sections below. writes to unimplemented register bits have no meaning or effect, and reads from unim- plemented bits always return a logic zero value. the module mapping bit of the sim configuration register (simcr) defines the most significant bit (addr23) of the address, shown in each register figure as y (y = $7 or $f). this bit, concatenated with the rest of the address given, forms the absolute address of each register. refer to the sim section of this technical summary for more information about how the state of mm affects the system. 5.3.1 global registers the qsm global registers contain system parameters used by both the qspi and the sci submodules. these registers contain the bits and fields used to configure the qsm. the qsmcr contains parameters for the qsm/cpu/intermodule bus (imb) interface. stop ?stop enable 0 = normal qsm clock operation 1 = qsm clock operation stopped stop places the qsm in a low-power state by disabling the system clock in most parts of the module. the qsmcr is the only register guaranteed to be readable while stop is asserted. the qspi ram is not readable. however, writes to ram or any register are guaranteed to be valid while stop is assert- ed. stop can be negated by the cpu and by reset. the system software must stop each submodule before asserting stop to avoid complications at re- start and to avoid data corruption. the sci submodule receiver and transmitter should be disabled, and the operation should be verified for completion before asserting stop. the qspi submodule should be stopped by asserting the halt bit in spcr3 and by asserting stop after the halta flag is set. frz1 ?freeze 1 0 = ignore the freeze signal on the imb 1 = halt the qspi (on a transfer boundary) frz1 determines what action is taken by the qspi when the freeze signal of the imb is asserted. freeze is asserted whenever the cpu enters the background mode. frz0 ?freeze 0 reserved bits [12:8] ?not implemented supv ?supervisor/unrestricted 0 = user access 1 = supervisor access supv defines the assignable qsm registers as either supervisor-only data space or unrestricted data space. iarb ?interrupt arbitration identification number the iarb field is used to arbitrate between simultaneous interrupt requests of the same priority. each module that can generate interrupt requests must be assigned a unique, non-zero iarb field value. re- fer to 3.8 interrupts for more information. qsmcr ?qsm configuration register $yffc00 15 14 13 12 11 10 9 8 7 6 5 4 3 0 stop frz1 frz0 0 0 0 0 0 supv 0 0 0 iarb reset: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
motorola mc68331 54 mc68331ts/d qtest ?qsm test register $yffc02 qtest is used during factory testing of the qsm. accesses to qtest must be made while the mcu is in test mode. qilr determines the priority level of interrupts requested by the qsm and the vector used when an in- terrupt is acknowledged. ilqspi ?interrupt level for qspi ilqspi determines the priority of qspi interrupts. this field must be given a value between $0 (inter- rupts disabled) to $7 (highest priority). ilsci ?interrupt level of sci ilsci determines the priority of sci interrupts. this field must be given a value between $0 (interrupts disabled) to $7 (highest priority). if ilqspi and ilsci are the same nonzero value, and both submodules simultaneously request inter- rupt service, qspi has priority. qivr determines which two vector numbers in the exception vector table are to be used for qsm inter- rupts. the seven msb of a user-defined vector number ($40?ff) must be written into the intv field during initialization. the value of intv0 is supplied by the qsm when an interrupt service request is acknowledged. during an interrupt-acknowledge cycle, intv[7:1] are driven on data[7:1] imb lines. data0 is negated for an sci interrupt and asserted for a qspi interrupt. writes to intv0 have no meaning or effect. reads of intv0 return a value of one. at reset, qivr is initialized to $0f, which corresponds to the uninitialized interrupt vector in the excep- tion table. 5.3.2 pin control registers the qsm uses nine pins, eight of which form a parallel port (portqs) on the mcu. although these pins are used by the serial subsystems, any pin can alternately be assigned as general-purpose i/o on a pin-by-pin basis. pins used for general-purpose i/o must not be assigned to the qspi by register pqspar. to avoid driving incorrect data, the first byte to be output must be written before ddrqs is configured. ddrqs must then be written to determine the direction of data flow and to output the value contained in register portqs. subsequent data for output is written to portqs. qilr ?qsm interrupt levels register $yffc04 15 14 13 11 10 8 7 0 0 0 ilqspi ilsci qivr reset: 0 0 0 0 0 0 0 0 qivr ?qsm interrupt vector register $yffc05 15 8 7 0 qilr intv reset: 0 0 0 0 1 1 1 1
mc68331 motorola mc68331ts/d 55 portqs latches i/o data. writes drive pins defined as outputs. reads return data present on the pins. to avoid driving undefined data, first write a byte to portqs, then configure ddrqs. clearing a bit in the pqspar assigns the corresponding pin to general-purpose i/o; setting a bit as- signs the pin to the qspi. the pqspar does not affect operation of the sci. notes: 1. pqs2 is a digital i/o pin unless the spi is enabled (spe in spcr1 set), in which case it becomes spi serial clock sck. 2. pqs7 is a digital i/o pin unless the sci transmitter is enabled (te in sccr1 = 1), in which case it be- comes sci serial output txd. portqs ?port qs data register $yffc14 15 8 7 6 5 4 3 2 1 0 not used pqs7 pqs6 pqs5 pqs4 pqs3 pqs2 pqs1 pqs0 reset: 0 0 0 0 0 0 0 0 pqspar ?port qs pin assignment register $yffc16 ddrqs ?port qs data direction register $yffc17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 pqspa6 pqspa5 pqspa4 pqspa3 0 pqspa1 pqspa0 ddqs7 ddqs6 ddqs5 ddqs4 ddqs3 ddqs2 ddqs1 ddqs0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 23 qspar pin assignments pqspar field pqspar bit pin function pqspa0 0 1 pqs0 miso pqspa1 0 1 pqs1 mosi pqspa2 0 1 pqs2 1 sck pqspa3 0 1 pqs3 pcs0/ss pqspa4 0 1 pqs4 pcs1 pqspa5 0 1 pqs5 pcs2 pqspa6 0 1 pqs6 pcs3 pqspa7 0 1 pqs7 2 txd
motorola mc68331 56 mc68331ts/d ddrqs determines whether pins are inputs or outputs. clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. ddrqs affects both qspi function and i/o function. notes: 1. pqs2 is a digital i/o pin unless the spi is enabled (spe in spcr1 set), in which case it becomes spi serial clock sck. 2. pqs7 is a digital i/o pin unless the sci transmitter is enabled (te in sccr1 = 1), in which case it becomes sci serial output txd. ddrqs determines the direction of the txd pin only when the sci transmitter is disabled. when the sci transmitter is enabled, the txd pin is an output. 5.4 qspi submodule the qspi submodule communicates with external devices through a synchronous serial bus. the qspi is fully compatible with the serial peripheral interface (spi) systems found on other motorola products. a block diagram of the qspi is shown below. table 24 effect of ddrqs on qsm pin function qsm pin mode ddrqs bit bit state pin function miso master ddq0 0 serial data input to qspi 1 disables data input slave 0 disables data output 1 serial data output from qspi mosi master ddq1 0 disables data output 1 serial data output from qspi slave 0 serial data input to qspi 1 disables data input sck 1 master ddq2 0 disables clock output 1 clock output from qspi slave 0 clock input to qspi 1 disables clock input pcs0/ss master ddq3 0 assertion causes mode fault 1 chip-select output slave 0 qspi slave select input 1 disables select input pcs[3:1] master ddq[4:6 ] 0 disables chip-select output 1 chip-select output slave 0 inactive 1 inactive txd 2 transmit ddq7 x serial data output from sci rxd receive none na serial data input to sci
mc68331 motorola mc68331ts/d 57 figure 13 qspi block diagram 5.4.1 qspi pins seven pins are associated with the qspi. when not needed for a qspi application, they can be con- figured as general-purpose i/o pins. the pcs0/ss pin can function as a peripheral chip select output, slave select input, or general-purpose i/o. refer to the following table for qspi input and output pins and their functions. qspi block control registers end queue pointer queue pointer status register delay counter comparator programmable logic array 80-byte qspi ram chip select command done 4 4 2 baud rate generator pcs[2:1] pcs0/ss miso mosi sck m s m s 8/16-bit shift register rx/tx data register msb lsb 4 4 queue control block control logic a d d r e s s r e g i s t e r
motorola mc68331 58 mc68331ts/d 5.4.2 qspi registers the programmer's model for the qspi submodule consists of the qsm global and pin control registers, four qspi control registers, one status register, and the 80-byte qspi ram. the cpu can read and write to registers and ram. the four control registers must be initialized before the qspi is enabled to ensure defined operation. spcr1 should be written last because it contains qspi enable bit spe. asserting this bit starts the qspi. the qspi control registers are reset to a de- fined state and can then be changed by the cpu. reset values are shown below each register. refer to the following memory map of the qspi. writing a different value into any control register except spcr2 while the qspi is enabled disrupts op- eration. spcr2 is buffered to prevent disruption of the current serial transfer. after completion of the current serial transfer, the new spcr2 values become effective. writing the same value into any control register except spcr2 while the qspi is enabled has no effect on qspi operation. rewriting newqp in spcr2 causes execution to restart at the designated location. spcr0 contains parameters for configuring the qspi before it is enabled. the cpu can read and write this register. the qsm has read-only access. pin names mnemonics mode function master in slave out miso master slave serial data input to qspi serial data output from qspi master out slave in mosi master slave serial data output from qspi serial data input to qspi serial clock sck master slave clock output from qspi clock input to qspi peripheral chip selects pcs[3:1] master select peripherals peripheral chip select slave select pcs0 ss master master slave selects peripheral causes mode fault initiates serial transfer address name usage $yffc18 spcr0 qspi control register 0 $yffc1a spcr1 qspi control register 1 $yffc1c spcr2 qspi control register 2 $yffc1e spcr3 qspi control register 3 $yffc1f spsr qspi status register $yffd00 ram qspi receive data (16 words) $yffd20 ram qspi transmit data (16 words) $yffd40 ram qspi command control (8 words) spcr0 ?qspi control register 0 $yffc18 15 14 13 10 9 8 7 0 mstr womq bits cpol cpha spbr reset: 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
mc68331 motorola mc68331ts/d 59 mstr ?master/slave mode select 0 = qspi is a slave device and only responds to externally generated serial data. 1 = qspi is system master and can initiate transmission to external spi devices. mstr configures the qspi for either master or slave mode operation. this bit is cleared on reset and may only be written by the cpu. womq ?wired-or mode for qspi pins 0 = outputs have normal mos drivers. 1 = pins designated for output by ddrqs have open-drain drivers. womq allows the wired-or function to be used on qspi pins, regardless of whether they are used as general-purpose outputs or as qspi outputs. womq affects the qspi pins regardless of whether the qspi is enabled or disabled. bits ?bits per transfer in master mode, when bitse in a command is set, the bits field determines the number of data bits transferred. when bitse is cleared, eight bits are transferred. reserved values default to eight bits. bitse is not used in slave mode. the following table shows the number of bits per transfer. cpol ?clock polarity 0 = the inactive state value of sck is logic level zero. 1 = the inactive state value of sck is logic level one. cpol is used to determine the inactive state value of the serial clock (sck). it is used with cpha to produce a desired clock/data relationship between master and slave devices. cpha ?clock phase 0 = data is captured on the leading edge of sck and changed on the following edge of sck. 1 = data is changed on the leading edge of sck and captured on the following edge of sck. cpha determines which edge of sck causes data to change and which edge causes data to be cap- tured. cpha is used with cpol to produce a desired clock/data relationship between master and slave devices. cpha is set at reset. bits bits per transfer 0000 16 0001 reserved 0010 reserved 0011 reserved 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15
motorola mc68331 60 mc68331ts/d spbr ?serial clock baud rate the qspi uses a modulus counter to derive sck baud rate from the mcu system clock. baud rate is selected by writing a value from 2 to 255 into the spbr field. the following equation determines the sck baud rate: sck baud rate = system clock/(2spbr) or spbr = system clock/(2sck)(baud rate desired) where spbr equals {2, 3, 4,..., 255} giving spbr a value of zero or one disables the baud rate generator. sck is disabled and assumes its inactive state value. no serial transfers occur. at reset, baud rate is initialized to one eighth of the sys- tem clock frequency. spcr1 contains parameters for configuring the qspi before it is enabled. the cpu can read and write this register, but the qsm has read access only, except for spe, which is automatically cleared by the qspi after completing all serial transfers, or when a mode fault occurs. spe ?qspi enable 0 = qspi is disabled. qspi pins can be used for general-purpose i/o. 1 = qspi is enabled. pins allocated by pqspar are controlled by the qspi. dsckl ?delay before sck when the dsck bit in command ram is set, this field determines the length of delay from pcs valid to sck transition. pcs can be any of the four peripheral chip-select pins. the following equation deter- mines the actual delay before sck: pcs to sck delay = [dsckl/system clock] where dsckl equals {1, 2, 3,..., 127}. when the dsck value of a queue entry equals zero, then dsckl is not used. instead, the pcs valid- to-sck transition is one-half sck period. dtl ?length of delay after transfer when the dt bit in command ram is set, this field determines the length of delay after serial transfer. the following equation is used to calculate the delay: delay after transfer = [(32dtl)/system clock] where dtl equals {1, 2, 3,..., 255}. a zero value for dtl causes a delay-after-transfer value of 8192/system clock. if dt equals zero, a standard delay is inserted. standard delay after transfer = [17/system clock] delay after transfer can be used to provide a peripheral deselect interval. a delay can also be inserted between consecutive transfers to allow serial a/d converters to complete conversion. spcr1 ?qspi control register 1 $yffc1a 15 14 8 7 0 spe dsckl dtl reset: 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
mc68331 motorola mc68331ts/d 61 spcr2 contains qspi configuration parameters. the cpu can read and write this register; the qsm has read access only. writes to spcr2 are buffered. a write to spcr2 that changes a bit value while the qspi is operating is ineffective on the current serial transfer, but becomes effective on the next se- rial transfer. reads of spcr2 return the current value of the register, not of the buffer. spifie ?spi finished interrupt enable 0 = qspi interrupts disabled 1 = qspi interrupts enabled spifie enables the qspi to generate a cpu interrupt upon assertion of the status flag spif. wren ?wrap enable 0 = wraparound mode disabled 1 = wraparound mode enabled wren enables or disables wraparound mode. wrto ?wrap to when wraparound mode is enabled, after the end of queue has been reached, wrto determines which address the qspi executes. bit 12 ?not implemented endqp ?ending queue pointer this field contains the last qspi queue address. bits [7:4] ?not implemented newqp ?new queue pointer value this field contains the first qspi queue address. spcr3 contains qspi configuration parameters. the cpu can read and write spcr3, but the qsm has read-only access. bits [15:11] ?not implemented loopq ?qspi loop mode 0 = feedback path disabled 1 = feedback path enabled loopq controls feedback on the data serializer for testing. hmie ?halta and modf interrupt enable 0 = halta and modf interrupts disabled 1 = halta and modf interrupts enabled hmie controls cpu interrupts caused by the halta status flag or the modf status flag in spsr. spcr2 ?qspi control register 2 $yffc1c 15 14 13 12 11 8 7 6 5 4 3 0 spifie wren wrto 0 endqp 0 0 0 0 newqp reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spcr3 ?qspi control register 3 $yffc1e 15 14 13 12 11 10 9 8 7 0 0 0 0 0 0 loopq hmie halt spsr reset: 0 0 0 0 0 0 0 0
motorola mc68331 62 mc68331ts/d halt ?halt 0 = halt not enabled 1 = halt enabled when halt is asserted, the qspi stops on a queue boundary. it is in a defined state from which it can later be restarted. spsr contains qspi status information. only the qspi can assert the bits in this register. the cpu reads this register to obtain status information and writes it to clear status flags. spif ?qspi finished flag 0 = qspi not finished 1 = qspi finished spif is set after execution of the command at the address in endqp. modf ?mode fault flag 0 = normal operation 1 = another spi node requested to become the network spi master while the qspi was enabled in master mode (ss input taken low). the qspi asserts modf when the qspi is the serial master (mstr = 1) and the ss input pin is negat- ed by an external driver. halta ?halt acknowledge flag 0 = qspi not halted 1 = qspi halted halta is asserted when the qspi halts in response to cpu assertion of halt. bit 4 ?not implemented cptqp ?completed queue pointer cptqp points to the last command executed. it is updated when the current command is complete. when the first command in a queue is executing, cptqp contains either the reset value ($0) or a point- er to the last command completed in the previous queue. 5.4.3 qspi ram the qspi contains an 80-byte block of dual-access static ram that is used by both the qspi and the cpu. the ram is divided into three segments: receive data, transmit data, and command control data. receive data is information received from a serial device external to the mcu. transmit data is infor- mation stored by the cpu for transmission to an external peripheral. command control data is used to perform the transfer. refer to the following illustration of the organization of the ram. spsr ?qspi status register $yffc1f 15 8 7 6 5 4 3 0 spcr3 spif modf halta 0 cptqp reset: 0 0 0 0 0 0 0 0
mc68331 motorola mc68331ts/d 63 figure 14 qspi ram once the cpu has set up the queue of qspi commands and enabled the qspi, the qspi can operate independently of the cpu. the qspi executes all of the commands in its queue, sets a flag indicating that it is finished, and then either interrupts the cpu or waits for cpu intervention. it is possible to ex- ecute a queue of commands repeatedly without cpu intervention. rr[0:f] ?receive data ram $yffd00 data received by the qspi is stored in this segment. the cpu reads this segment to retrieve data from the qspi. data stored in receive ram is right-justified. unused bits in a receive queue entry are set to zero by the qspi upon completion of the individual queue entry. the cpu can access the data using byte, word, or long-word addressing. the cptqp value in spsr shows which queue entries have been executed. the cpu uses this infor- mation to determine which locations in receive ram contain valid data before reading them. tr[0:f] ?transmit data ram $yffd20 data that is to be transmitted by the qspi is stored in this segment. the cpu usually writes one word of data into this segment for each queue command to be executed. information to be transmitted must be written to transmit data ram in a right-justified format. the qspi cannot modify information in the transmit data ram. the qspi copies the information to its data serial- izer for transmission. information remains in transmit ram until overwritten. *the pcs0 bit represents the dual-function pcs0/ss . command ram is used by the qspi when in master mode. the cpu writes one byte of control infor- mation to this segment for each qspi command to be executed. the qspi cannot modify information in command ram. cr[0:f] ?command ram $yffd40 7 6543210 cont bitse dt dsck pcs3 pcs2 pcs1 pcs0* ?????? cont bitse dt dsck pcs3 pcs2 pcs1 pcs0* receive ram transmit ram 500 51e 520 53e word 540 54f command ram byte word rr0 rr1 rr2 rrd rre rrf tr0 tr1 tr2 trd tre trf cr0 cr1 cr2 crd cre crf
motorola mc68331 64 mc68331ts/d command ram consists of 16 bytes. each byte is divided into two fields. the peripheral chip-select field enables peripherals for transfer. the command control field provides transfer options. a maximum of 16 commands can be in the queue. queue execution by the qspi proceeds from the address in newqp through the address in endqp. (both of these fields are in spcr2.) cont ?continue 0 = control of chip selects returned to portqs after transfer is complete. 1 = peripheral chip selects remain asserted after transfer is complete. bitse ?bits per transfer enable 0 = 8 bits 1 = number of bits set in bits field of spcr0 dt ?delay after transfer the qspi provides a variable delay at the end of serial transfer to facilitate the interface with peripherals that have a latency requirement. the delay between transfers is determined by the spcr1 dtl field. dsck ?pcs to sck delay 0 = pcs valid to sck transition is one-half sck. 1 = spcr1 dsckl field specifies delay from pcs valid to sck. pcs[3:0] ?peripheral chip select use peripheral chip-select bits to select an external device for serial data transfer. more than one pe- ripheral chip select can be activated at a time, and more than one peripheral chip can be connected to each pcs pin, provided that proper fanout is observed. ss ?slave mode select initiates slave mode serial transfer. if ss is taken low when the qspi is in master mode, a mode fault will be generated. 5.4.4 operating modes the qspi operates in either master or slave mode. master mode is used when the mcu originates data transfers. slave mode is used when an external device initiates serial transfers to the mcu through the qspi. switching between the modes is controlled by mstr in spcr0. before entering either mode, appropriate qsm and qspi registers must be properly initialized. in master mode, the qspi executes a queue of commands defined by control bits in each command ram queue entry. chip-select pins are activated, data is transmitted from transmit ram and received into receive ram. in slave mode, operation proceeds in response to ss pin activation by an external bus master. opera- tion is similar to master mode, but no peripheral chip selects are generated, and the number of bits transferred is controlled in a different manner. when the qspi is selected, it automatically executes the next queue transfer to exchange data with the external device correctly. although the qspi inherently supports multimaster operation, no special arbitration mechanism is pro- vided. a mode fault flag (modf) indicates a request for spi master arbitration. system software must provide arbitration. note that unlike previous spi systems, mstr is not cleared by a mode fault being set, nor are the qspi pin output drivers disabled. the qspi and associated output drivers must be dis- abled by clearing spe in spcr1. 5.5 sci submodule the sci submodule is used to communicate with external devices through an asynchronous serial bus. the sci is fully compatible with the sci systems found on other motorola mcus, such as the m68hc11 and m68hc05 families.
mc68331 motorola mc68331ts/d 65 5.5.1 sci pins there are two unidirectional pins associated with the sci. the sci controls the transmit data (txd) pin when enabled, whereas the receive data (rxd) pin remains a dedicated input pin to the sci. txd is available as a general-purpose i/o pin when the sci transmitter is disabled. when used for i/o, txd can be configured either as input or output, as determined by qsm register ddrqs. the following table shows sci pins and their functions. 5.5.2 sci registers the sci programming model includes qsm global and pin control registers, and four sci registers. there are two sci control registers, one status register, and one data register. all registers can be read or written at any time by the cpu. changing the value of sci control bits during a transfer operation may disrupt operation. before chang- ing register values, allow the transmitter to complete the current transfer, then disable the receiver and transmitter. status flags in the scsr may be cleared at any time. sccr0 contains a baud rate selection parameter. baud rate must be set before the sci is enabled. the cpu can read and write this register at any time. bits [15:13] ?not implemented scbr ?baud rate sci baud rate is programmed by writing a 13-bit value to br. the baud rate is derived from the mcu system clock by a modulus counter. the sci receiver operates asynchronously. an internal clock is necessary to synchronize with an in- coming data stream. the sci baud rate generator produces a receiver sampling clock with a frequency 16 times that of the expected baud rate of the incoming data. the sci determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper po- sitions within the bit period. receiver sampling rate is always 16 times the frequency of the sci baud rate, which is calculated as follows: sci baud rate = system clock/(32scbr) or scbr = system clock(32sck)(baud rate desired) where scbr is in the range {1, 2, 3, ..., 8191} writing a value of zero to scbr disables the baud rate generator. the following table lists the scbr settings for standard and maximum baud rates using 16.78-mhz and 20.97-mhz system clocks. pin names mnemonics mode function receive data rxd receiver disabled receiver enabled not used serial data input to sci transmit data txd transmitter disabled transmitter enabled general-purpose i/o serial data output from sci sccr0 ?sci control register 0 $yffc08 15 14 13 12 0 0 0 0 scbr reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
motorola mc68331 66 mc68331ts/d *a rate of 64 baud is not available with a 20.97-mhz system clock. to achieve this rate, the syncr can be pro- grammed to generate a lower system clock rate. sccr1 contains sci configuration parameters. the cpu can read and write this register at any time. the sci can modify rwu in some circumstances. in general, interrupts enabled by these control bits are cleared by reading scsr, then reading (receiver status bits) or writing (transmitter status bits) scdr. bit 15 ?not implemented loops ?loop mode 0 = normal sci operation, no looping, feedback path disabled 1 = test sci operation, looping, feedback path enabled loops controls a feedback path on the data serial shifter. when loop mode is enabled, sci transmitter output is fed back into the receive serial shifter. txd is asserted (idle line). both transmitter and receiver must be enabled before entering loop mode. woms ?wired-or mode for sci pins 0 = if configured as an output, txd is a normal cmos output. 1 = if configured as an output, txd is an open-drain output. woms determines whether the txd pin is an open-drain output or a normal cmos output. this bit is used only when txd is an output. if txd is used as a general-purpose input pin, woms has no effect. ilt ?idle-line detect type 0 = short idle-line detect (start count on first one) 1 = long idle-line detect (start count on first one after stop bit(s)) table 25 sci baud rates nominal baud rate actual rate with 16.78-mhz clock scbr value actual rate with 20.97-mhz clock scbr value 64* 64.0 $1fff 110 110.0 $129e 110.0 $1745 300 299.9 $06d4 300.1 $0888 600 599.9 $036a 600.1 $0444 1200 1199.7 $0165 1200.3 $0222 2400 2405.0 $00da 2400.6 $0111 4800 4810.0 $006d 4783.6 $0089 9600 9532.5 $0037 9637.6 $0044 19200 19418.1 $0016 19275.3 $0022 38400 37449.1 $000e 38550.6 $0011 76800 74898.3 $0007 72817.8 $0009 maximum rate 524288.0 $0001 655360.0 $0001 sccr1 ?sci control register 1 $yffc0a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 scbr reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
mc68331 motorola mc68331ts/d 67 pt ?parity type 0 = even parity 1 = odd parity when parity is enabled, pt determines whether parity is even or odd for both the receiver and the trans- mitter. pe ?parity enable 0 = sci parity disabled 1 = sci parity enabled pe determines whether parity is enabled or disabled for both the receiver and the transmitter. if the re- ceived parity bit is not correct, the sci sets the pf error flag in scsr. when pe is set, the most significant bit (msb) of the data field is used for the parity function, which re- sults in either seven or eight bits of user data, depending on the condition of m bit. the following table lists the available choices. m ?mode select 0 = sci frame: 1 start bit, 8 data bits, 1 stop bit (10 bits total) 1 = sci frame: 1 start bit, 9 data bits, 1 stop bit (11 bits total) wake ?wakeup by address mark 0 = sci receiver awakened by idle-line detection 1 = sci receiver awakened by address mark (last bit set) tie ?transmit interrupt enable 0 = sci tdre interrupts inhibited 1 = sci tdre interrupts enabled tcie ?transmit complete interrupt enable 0 = sci tc interrupts inhibited 1 = sci tc interrupts enabled rie ?receiver interrupt enable 0 = sci rdrf interrupt inhibited 1 = sci rdrf interrupt enabled ilie ?idle-line interrupt enable 0 = sci idle interrupts inhibited 1 = sci idle interrupts enabled te ?transmitter enable 0 = sci transmitter disabled (txd pin may be used as i/o) 1 = sci transmitter enabled (txd pin dedicated to sci transmitter) the transmitter retains control of the txd pin until completion of any character transfer in progress when te is cleared. re ?receiver enable 0 = sci receiver disabled (status bits inhibited) 1 = sci receiver enabled m pe result 0 0 8 data bits 0 1 7 data bits, 1 parity bit 1 0 9 data bits 1 1 8 data bits, 1 parity bit
motorola mc68331 68 mc68331ts/d rwu ?receiver wakeup 0 = normal receiver operation (received data recognized) 1 = wakeup mode enabled (received data ignored until awakened) setting rwu enables the wakeup function, which allows the sci to ignore received data until awakened by either an idle line or address mark (as determined by wake). when in wakeup mode, the receiver status flags are not set, and interrupts are inhibited. this bit is cleared automatically (returned to normal mode) when the receiver is awakened. sbk ?send break 0 = normal operation 1 = break frame(s) transmitted after completion of current frame sbk provides the ability to transmit a break code from the sci. if the sci is transmitting when sbk is set, it will transmit continuous frames of zeros after it completes the current frame, until sbk is cleared. if sbk is toggled (one to zero in less than one frame interval), the transmitter sends only one or two break frames before reverting to idle line or beginning to send data. scsr contains flags that show sci operational conditions. these flags can be cleared either by hard- ware or by a special acknowledgment sequence. the sequence consists of scsr read with flags set, followed by scdr read (write in the case of tdre and tc). a long-word read can consecutively access both scsr and scdr. this action clears receive status flag bits that were set at the time of the read, but does not clear tdre or tc flags. if an internal sci signal for setting a status bit comes after the cpu has read the asserted status bits, but before the cpu has written or read register scdr, the newly set status bit is not cleared. scsr must be read again with the bit set. also, scdr must be written or read before the status bit is cleared. reading either byte of scsr causes all 16 bits to be accessed. any status bit already set in either byte will be cleared on a subsequent read or write of register scdr. tdre ?transmit data register empty flag 0 = register tdr still contains data to be sent to the transmit serial shifter. 1 = a new character can now be written to register tdr. tdre is set when the byte in register tdr is transferred to the transmit serial shifter. if tdre is zero, transfer has not occurred and a write to tdr will overwrite the previous value. new data is not trans- mitted if tdr is written without first clearing tdre. tc ?transmit complete flag 0 = sci transmitter is busy 1 = sci transmitter is idle tc is set when the transmitter finishes shifting out all data, queued preambles (mark/idle line), or queued breaks (logic zero). the interrupt can be cleared by reading scsr when tc is set and then by writing the transmit data register (tdr) of scdr. rdrf ?receive data register full flag 0 = register rdr is empty or contains previously read data. 1 = register rdr contains new data. rdrf is set when the content of the receive serial shifter is transferred to the rdr. if one or more errors are detected in the received word, flag(s) nf, fe, and/or pf are set within the same clock cycle. scsr ?sci status register $yffc0c 15 9 8 7 6 5 4 3 2 1 0 not used tdre tc rdrf raf idle or nf fe pf reset: 1 1 0 0 0 0 0 0 0
mc68331 motorola mc68331ts/d 69 raf ?receiver active flag 0 = sci receiver is idle 1 = sci receiver is busy raf indicates whether the sci receiver is busy. it is set when the receiver detects a possible start bit and is cleared when the chosen type of idle line is detected. raf can be used to reduce collisions in systems with multiple masters. idle ?idle-line detected flag 0 = sci receiver did not detect an idle-line condition. 1 = sci receiver detected an idle-line condition. idle is disabled when rwu in sccr1 is set. idle is set when the sci receiver detects the idle-line condition specified by ilt in sccr1. if cleared, idle will not set again until after rdrf is set. rdrf is set when a break is received, so that a subsequent idle line can be detected. or ?overrun error flag 0 = rdrf is cleared before new data arrives. 1 = rdrf is not cleared before new data arrives. or is set when a new byte is ready to be transferred from the receive serial shifter to the rdr, and rdrf is still set. data transfer is inhibited until or is cleared. previous data in rdr remains valid, but data received during overrun condition (including the byte that set or) is lost. nf ?noise error flag 0 = no noise detected on the received data 1 = noise occurred on the received data nf is set when the sci receiver detects noise on a valid start bit, on any data bit, or on a stop bit. it is not set by noise on the idle line or on invalid start bits. each bit is sampled three times. if none of the three samples are the same logic level, the majority value is used for the received data value, and nf is set. nf is not set until an entire frame is received and rdrf is set. fe ?framing error flag 0 = no framing error on the received data. 1 = framing error or break occurred on the received data. fe is set when the sci receiver detects a zero where a stop bit was to have occurred. fe is not set until the entire frame is received and rdrf is set. a break can also cause fe to be set. it is possible to miss a framing error if rxd happens to be at logic level one at the time the stop bit is expected. pf ?parity error flag 0 = no parity error on the received data 1 = parity error occurred on the received data pf is set when the sci receiver detects a parity error. pf is not set until the entire frame is received and rdrf is set. scdr contains two data registers at the same address. receive data register (rdr) is a read-only reg- ister that contains data received by the sci. the data comes into the receive serial shifter and is trans- ferred to rdr. transmit data register (tdr) is a write-only register that contains data to be transmitted. the data is first written to tdr, then transferred to the transmit serial shifter, where additional format bits are added before transmission. r[7:0]/t[7:0] contain either the first eight data bits received when scdr is read, or the first eight data bits to be transmitted when scdr is written. r8/t8 are used when the sci is configured for 9-bit operation. when it is configured for 8-bit operation, they have no meaning or effect. scdr ?sci data register $yffc0e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 r8/t8 r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 reset: 0 0 0 0 0 0 0 u u u u u u u u u
motorola mc68331 70 mc68331ts/d 6 general-purpose timer module the 11-channel general-purpose timer (gpt) is used in systems where a moderate level of cpu control is required. the gpt consists of a capture/compare unit, a pulse accumulator, and two pulse-width modulators. a bus interface unit connects the gpt to the intermodule bus. figure 15 gpt block diagram 6.1 overview the capture/compare unit features three input capture channels, four output compare channels, and one channel that can be selected as an input capture or output compare channel. these channels share a 16-bit free-running counter (tcnt) which derives its clock from a nine-stage prescaler or from the ex- ternal clock input signal, pclk. pulse accumulator channel logic includes an 8-bit counter; the pulse accumulator can operate in either event counting mode or gated time accumulation mode. pulse-width modulator outputs are periodic waveforms whose duty cycles can be independently select- ed and modified by user software. the pwm circuits share a 16-bit free-running counter that can be clocked by the same nine-stage prescaler used by the capture/compare unit or by the pclk input. all gpt pins can also be used for general-purpose input/output. the input capture and output compare pins form a bidirectional 8-bit parallel port (portgp). pwm pins are outputs only. pai and pclk pins are inputs only. gpt input capture/output compare pins are bidirectional and can be used to form an 8-bit parallel port. the pulse-width modulator outputs can be used as general-purpose outputs. the pai and pclk inputs can be used as general-purpose inputs. the gpt control register address map is shown below. the ?ccess?column in the gpt address map indicates which registers are accessible only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege level, according to the value of the supv bit in the gptmcr. gpt block pulse accumulator pwm unit bus interface imb capture/compare unit prescaler ic1/pgp0 ic2/pgp1 ic3/pgp2 pclk pwmb pwma pai ic4/oc5/oc1/pgp7 oc4/oc1/pgp6 oc3/oc1/pgp5 oc2/oc1/pgp4 oc1/pgp3
mc68331 motorola mc68331ts/d 71 y = m111, where m is the logic state of the modmap (mm) bit in simcr. 6.2 capture/compare unit the capture/compare unit features three input capture channels, four output compare channels, and one input capture/output compare channel (function selected by control register). these channels share a 16-bit free-running counter (tcnt), which derives its clock from seven stages of a 9-stage prescaler or from external clock input pclk. this section, which is similar to the timer found on the mc68hc11f1, also contains one pulse accumulator channel. the pulse accumulator logic includes its own 8-bit counter and can operate in either event counting mode or gated time accumulation mode. refer to the following block diagrams of the gpt timer and prescaler. table 26 gpt address map access address 15 8 7 0 s $yff900 gpt module configuration (gptmcr) s $yff902 (reserved for test) s $yff904 interrupt configuration (icr) u $yff906 pgp data direction (ddrgp) pgp data (portgp) u $yff908 oc1 action mask (oc1m) oc1 action data (oc1d) u $yff90a timer counter (tcnt) u $yff90c pa control (pactl) pa counter (pacnt) u $yff90e input capture 1 (tic1) u $yff910 input capture 2 (tic2) u $yff912 input capture 3 (tic3) u $yff914 output compare 1 (toc1) u $yff916 output compare 2 (toc2) u $yff918 output compare 3 (toc3) u $yff91a output compare 4 (toc4) u $yff91c input capture 4/output compare 5 (ti4/o5) u $yff91e timer control 1 (tctl1) timer control 2 (tctl2) u $yff920 timer mask 1 (tmsk1) timer mask 2 (tmsk2) u $yff922 timer flag 1 (tflg1) timer flag 2 (tflg2) u $yff924 force compare (cforc) pwm control c (pwmc) u $yff926 pwm control a (pwma) pwm control b (pwmb) u $yff928 pwm count (pwmcnt) u $yff92a pwma buffer (pwmbufa) pwmb buffer (pwmbufb) u $yff92c gpt prescaler (prescl) $yff92e $yff93f not used
motorola mc68331 72 mc68331ts/d figure 16 gpt timer block diagram 16/32 cc block system clock 16-bit latch clk 8 7 6 5 4 bit 3 bit 4 bit 5 bit 6 bit 7 parallel port pin control oc1i oc2i oc3i oc4i i4/o5i tflg1 status flags foc1 foc2 foc3 foc4 foc5 oc1f oc2f oc3f oc4f i4/o5f i4/o5 16-bit comparator toc1 (hi) toc1 (lo) = 16-bit comparator toc2 (hi) toc2 (lo) = 16-bit comparator toc3 (hi) toc3 (lo) = 16-bit comparator toc4 (hi) toc4 (lo) = 16-bit comparator ti4/o5 (hi) ti4/o5 (lo) = 16-bit free running counter tcnt (hi) tcnt (lo) 9 toi tof interrupt requests prescaler ?divide by 4, 8, 16, 32, 64, 128, 256 cpr2 cpr1 16-bit timer bus oc5 ic4 1 2 3 bit 0 bit 1 bit 2 ic1i ic2i ic3i ic1f ic2f ic3f 16-bit latch tic1 (hi) tic1 (lo) clk 16-bit latch tic2 (hi) tic2 (lo) clk 16-bit latch tic3 (hi) tic3 (lo) clk tmsk1 interrupt enables cforc force output compare pin functions cpr0 1 of 8 select pclk ic4/oc5/ oc4/oc1 oc3/oc1 oc2/oc1 oc1 ic3 ic2 ic1 pgp0 pgp1 pgp2 pgp3 pgp4 pgp5 pgp6 pgp7 oc1
mc68331 motorola mc68331ts/d 73 figure 17 prescaler block diagram gpt pre block cpr2 cpr1 cpr0 to pulse accumulator to pulse accumulator to capture/ compare timer select divider ? 256 ? 128 ? 64 ? 32 ? 16 ? 8 ? 4 ? 64 ? 32 ? 16 ? 8 ? 4 ? 2 ? 128 ? 256 ? 512 system clock ? 512 ppr2 ppr1 ppr0 pwm unit to select ? 2 ? 4 ? 8 ? 16 ? 32 ? 64 ? 128 to pulse accumulator ext. synchronizer and digital filter ext. ext. pclk pin
motorola mc68331 74 mc68331ts/d figure 18 pwm unit block diagram 6.3 pulse-width modulator the pulse-width modulation submodule has two output pins. the outputs are periodic waveforms con- trolled by a single frequency whose duty cycles can be independently selected and modified by user software. each pwm can be independently programmed to run in fast or slow mode. the pwm unit has its own 16-bit free-running counter, which is clocked by an output of the nine-stage prescaler (the same prescaler used by the capture/compare unit) or by the clock input pin, pclk. 16/32 pwm block block zero detector 16-bit counter pwma register pwmb register pwmabuf register pwmbbuf register "a" comparator "b" comparator "a" multiplexer "b" multiplexer sfb bit sfa bit f1a bit f1b bit latch r s latch r s zero detector pwmb pin pwma pin from prescaler clock [14:0] 16-bit data bus 8-bit 8-bit
mc68331 motorola mc68331ts/d 75 6.4 gpt registers the gptmcr contains parameters for configuring the gpt. stop ?stop clocks 0 = internal clocks not shut down 1 = internal clocks shut down frz1 ?not implemented at this time frz0 ?freeze response 0 = ignore freeze 1 = freeze the current state of the gpt stopp ?stop prescaler 0 = normal operation 1 = stop prescaler and pulse accumulator from incrementing. ignore changes to input pins. incp ?increment prescaler 0 = has no meaning 1 = if stopp is asserted, increment prescaler once and clock input synchronizers once. supv ?supervisor/unrestricted data space 0 = registers with access controlled by supv bit are accessible from either user or supervisor priv- ilege level. 1 = registers with access controlled by supv bit are restricted to supervisor access only. iarb ?interrupt arbitration field the iarb field is used to arbitrate between simultaneous interrupt requests of the same priority. each module that can generate interrupt requests must be assigned a unique, non-zero iarb field value. re- fer to 3.8 interrupts for more information. mtr ?gpt module test register (reserved) $yff902 this address is currently unused and returns zeros if read. it is reserved for gpt factory test. ipa ?interrupt priority adjust specifies which gpt interrupt source is given highest internal priority ipl ?interrupt priority level specifies the priority level of interrupts generated by the gpt. ivba ?interrupt vector base address most significant nibble of interrupt vector number generated by the gpt when an interrupt service re- quest is acknowledged. gptmcr ?gpt module configuration register $yff900 15 14 13 12 11 10 9 8 7 6 5 4 3 0 stop frz1 frz0 stopp incp 0 0 0 supv 0 0 0 iarb reset: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 icr ?gpt interrupt configuration register $yff904 15 12 11 10 8 7 4 3 2 1 0 ipa 0 ipl ivba 0 0 0 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola mc68331 76 mc68331ts/d when gpt pins are used as an 8-bit port, ddrgp determines whether pins are input or output and portgp holds the 8-bit data. ddrgp[7:0] ?port gp data direction register 0 = input only 1 = output each bit in ddrgp determines whether the corresponding portgp bit is input or output. all oc outputs can be controlled by the action of oc1. oc1m contains a mask that determines which pins are affected. oc1d determines what the outputs are. oc1m[5:1] ?oc1 mask field 0 = corresponding output compare pin is not affected by oc1 compare. 1 = corresponding output compare pin is affected by oc1 compare. oc1m[5:1] correspond to oc[5:1]. oc1d[5:1] ?oc1 data field 0 = if oc1 mask bit is set, clear the corresponding output compare pin on oc1 match. 1 = if oc1 mask bit is set, set the corresponding output compare pin on oc1 match. oc1d[5:1] correspond to oc[5:1]. tcnt ?timer counter register $yff90a tcnt is the 16-bit free-running counter associated with the input capture, output compare, and pulse accumulator functions of the gpt module. pactl enables the pulse accumulator and selects either event counting or gated mode. in event count- ing mode, pacnt is incremented each time an event occurs. in gated mode, it is incremented by an internal clock. pais ?pai pin state (read only) paen ?pulse accumulator system enable 0 = pulse accumulator disabled 1 = pulse accumulator enabled ddrgp/portgp ?port gp data direction register/port gp data register $yff906 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ddgp7 ddgp6 ddgp5 ddgp4 ddgp3 ddgp2 ddgp1 ddgp0 pgp7 pgp6 pgp5 pgp4 pgp3 pgp2 pgp1 pgp0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 oc1m/oc1d ?oc1 action mask register/oc1 action data register $yff908 15 11 10 9 8 7 3 2 1 0 oc1m 0 0 0 oc1d 0 0 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pactl/pacnt ?pulse accumulator control register/counter $yff90c 15 14 13 12 11 10 9 8 7 0 pais paen pamod pedge pclks i4/o5 paclk pacnt reset: u 0 0 0 u 0 0 0 0 0 0 0 0 0 0 0
mc68331 motorola mc68331ts/d 77 pamod ?pulse accumulator mode 0 = external event counting 1 = gated time accumulation pedge ?pulse accumulator edge control the effects of pedge and pamod are shown in the following table. pclks ?pclk pin state (read only) i4/o5 ?input capture 4/output compare 5 0 = output compare 5 enabled 1 = input capture 4 enabled paclk[1:0] ?pulse accumulator clock select (gated mode) pacnt ?pulse accumulator counter 8-bit read/write counter used for external event counting or gated time accumulation. tic[1:3] ?input capture registers 1? $yff90e, $yff910, $yff912 the input capture registers are 16-bit read-only registers which are used to latch the value of tcnt when a specified transition is detected on the corresponding input capture pin. they are reset to $ffff. toc[1:4] ?output compare registers 1? $yff914, $yff916, $yff918, $yff91a the output compare registers are 16-bit read/write registers which can be used as output waveform controls or as elapsed time indicators. for output compare functions, they are written to a desired match value and compared against tcnt to control specified pin actions. they are reset to $ffff. ti4/o5 ?input capture 4/output compare 5 register $yff91c this register serves either as input capture register 4 or output compare register 5, depending on the state of i4/o5 in pactl. tctl1 determines output compare mode and output logic level. tctl2 determines the type of input capture to be performed. pamod pedge effect 0 0 pai falling edge increments counter 0 1 pai rising edge increments counter 1 0 zero on pai inhibits counting 1 1 one on pai inhibits counting paclk[1:0] pulse accumulator clock selected 00 system clock divided by 512 01 same clock used to increment tcnt 10 tof flag from tcnt 11 external clock, pclk tctl1/tctl2 ?timer control registers 1? $yff91e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 om5 ol5 om4 ol4 om3 ol3 om2 ol2 edge4 edge3 edge2 edge1 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola mc68331 78 mc68331ts/d om/ol[5:2] ?output compare mode bits and output compare level bits each pair of bits specifies an action to be taken when output comparison is successful. edge[4:1] ?input capture edge control bits each pair of bits configures input sensing logic for the corresponding input capture. tmsk1 enables oc and ic interrupts. tmsk2 controls pulse accumulator interrupts and tcnt func- tions. i4/o5i ?input capture 4/output compare 5 interrupt enable 0 = ic4/oc5 interrupt disabled 1 = ic4/oc5 interrupt requested when i4/o5f flag in tflg1 is set oci[4:1] ?output compare interrupt enable 0 = oc interrupt disabled 1 = oc interrupt requested when oc flag set oci[4:1] correspond to oc[4:1]. ici[3:1] ?input capture interrupt enable 0 = ic interrupt disabled 1 = ic interrupt requested when ic flag set ici[3:1] correspond to ic[3:1]. toi ?timer overflow interrupt enable 0 = timer overflow interrupt disabled 1 = interrupt requested when tof flag is set paovi ?pulse accumulator overflow interrupt enable 0 = pulse accumulator overflow interrupt disabled 1 = interrupt requested when paovf flag is set paii ?pulse accumulator input interrupt enable 0 = pulse accumulator interrupt disabled 1 = interrupt requested when paif flag is set cprout ?compare/capture unit clock output enable 0 = normal operation for oc1 pin 1 = tcnt clock driven out oc1 pin om/ol[5:2] action taken 00 timer disconnected from output logic 01 toggle ocx output line 10 clear ocx output line to 0 11 set ocx output line to 1 edge[4:1] configuration 00 capture disabled 01 capture on rising edge only 10 capture on falling edge only 11 capture on any (rising or falling) edge tmsk1/tmsk2 ?timer interrupt mask registers 1? $yff920 15 14 11 10 8 7 6 5 4 3 2 0 i4/o5i oci ici toi 0 paovi paii cprout cpr reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
mc68331 motorola mc68331ts/d 79 cpr[2:0] ?timer prescaler/pclk select field this field selects one of seven prescaler taps or pclk to be tcnt input. these registers show condition flags that correspond to various gpt events. if the corresponding inter- rupt enable bit in tmsk1/tmsk2 is set, an interrupt occurs. i4/o5f ?input capture 4/output compare 5 flag when i4/o5 in pactl is zero, this flag is set each time tcnt matches the value in toc5. when i4/o5 in pactl is one, the flag is set each time a selected edge is detected at the i4/o5 pin. ocf[4:1] ?output compare flags an output compare flag is set each time tcnt matches the corresponding toc register. ocf[4:1] cor- respond to oc[4:1]. icf[3:1] ?input capture flags a flag is set each time a selected edge is detected at the corresponding input capture pin. icf[3:1] cor- respond to ic[3:1]. tof ?timer overflow flag this flag is set each time tcnt advances from a value of $ffff to $0000. paovf ?pulse accumulator overflow flag this flag is set each time the pulse accumulator counter advances from a value of $ff to $00. paif ?pulse accumulator flag in event counting mode, this flag is set when an active edge is detected on the pai pin. in gated time accumulation mode, paif is set at the end of the timed period. cforc/pwmc ?compare force register/pwm control register c $yff924 setting a bit in cforc causes a specific output on oc or pwm pins. pwmc sets pwm operating con- ditions. cpr[2:0] system clock divide-by factor 000 4 001 8 010 16 011 32 100 64 101 128 110 256 111 pclk tflg1/tflg2 ?timer interrupt flag registers 1? $yff922 15 14 11 10 8 7 6 5 4 3 2 1 0 i4/o5f ocf icf tof 0 paovf paif 0 0 0 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 11 10 9 8 7 6 4 3 2 1 0 foc 0 fpwma fpwmb pprout ppr sfa sfb f1a f1b reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola mc68331 80 mc68331ts/d foc[5:1] ?force output compare 0 = has no meaning 1 = causes pin action programmed for corresponding oc pin, but the oc flag is not set. foc[5:1] correspond to oc[5:1]. fpwma ?force pwma value 0 = normal pwma operation 1 = the value of f1a is driven out on the pwma pin, regardless of the state of pprout. fpwmb ?force pwmb value 0 = normal pwmb operation 1 = the value of f1b is driven out on the pwmb pin. pprout ?pwm clock output enable 0 = normal pwm operation on pwma 1 = tcnt clock driven out pwma pin ppr[2:0] ?pwm prescaler/pclk select this field selects one of seven prescaler taps, or pclk, to be pwmcnt input. sfa ?pwma slow/fast select 0 = pwma period is 256 pwmcnt increments long. 1 = pwma period is 32768 pwmcnt increments long. sfb ?pwmb slow/fast select 0 = pwmb period is 256 pwmcnt increments long. 1 = pwmb period is 32768 pwmcnt increments long. the following table shows the effects of sf settings on pwm frequency for a 16.78-mhz system clock and a 20.97-mhz system clock. f1a ?force logic level one on pwma 0 = force logic level zero output on pwma pin 1 = force logic level one output on pwma pin ppr[2:0] system clock divide-by factor 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 pclk ppr[2:0] prescaler tap sfa/b = 0 sfa/b = 1 16.78 mhz 20.97 mhz 16.78 mhz 20.97 mhz 16.78 mhz 20.97 mhz 000 div 2 = 8.39 mhz div 2 = 10.5 mhz 32.8 khz 41 khz 256 hz 320 hz 001 div 4 = 4.19 mhz div 4 = 5.25 mhz 16.4 khz 20.5 khz 128 hz 160 hz 010 div 8 = 2.10 mhz div 8 = 2.62 mhz 8.19 khz 10.2 khz 64.0 hz 80.0 hz 011 div 16 = 1.05 mhz div 16 = 1.31 mhz 4.09 khz 5.15 khz 32.0 hz 40.0 hz 100 div 32 = 524 khz div 32 = 655 khz 2.05 khz 2.56 khz 16.0 hz 20.0 hz 101 div 64 = 262 khz div 64 = 328 khz 1.02 khz 1.28 khz 8.0 hz 10.0 hz 110 div 128 = 131 khz div 128 = 164 khz 512 hz 641 hz 4.0 hz 5.0 hz 111 pclk pclk pclk/256 pclk/256 pclk/32768 pclk/32768
mc68331 motorola mc68331ts/d 81 f1b ?force logic level one on pwmb 0 = force logic level zero output on pwmb pin 1 = force logic level one output on pwmb pin pwma/pwmb ?pwm control registers a/b $yff926, $yff927 these registers are associated with the pulse-width value of the pwm output on the corresponding pwm pin. a value of $00 loaded into one of these registers results in a continuously low output on the corresponding pin. a value of $80 results in a 50% duty cycle output. maximum value ($ff) selects an output that is high for 255/256 of the period. pwmcnt ?pwm count register $yff928 pwmcnt is the 16-bit free-running counter associated with the pwm functions of the gpt module. pwmbufa/b ?pwm buffer registers a/b $yff92a, $yff92b these read-only registers contain values associated with the duty cycles of the corresponding pwm. reset state is $0000. prescl ?gpt prescaler $yff92c the 9-bit prescaler value can be read from bits [8:0] at this address. bits [15:9] always read as zeros. reset state is $0000.
motorola mc68331 82 mc68331ts/d 7 summary of changes this is a complete revision, with complete reprint. all known errors in the publication have been correct- ed. the following summary lists significant changes. typographical errors that do not affect content are not annotated. page 2 revised ordering information. page 5 new block diagram drawn. page 6 new 132-pin assignment diagram drawn. page 7 new 144-pin assignment diagram drawn. page 8 new address map drawn. page 9-13 added signal description section. page 14-46 expanded and revised sim section. made all register diagrams and bit mnemonics consistent. incorporated new information concerning the system clock, resets, in- terrupts, and chip-select circuits. page 47-55 expanded and revised cpu section. made all register diagrams and bit mnemon- ics consistent. revised instruction set summary information. page 56-76 expanded and revised qsm section. made all register diagrams and bit mnemon- ics consistent. added information concerning spi and sci operation. page 77-89 expanded and revised gpt section. made all registerdiagrams and bit mnemonics consistent. added information concerning input capture, output compare, and pwm operation.
mc68331 motorola mc68331ts/d 83
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mc68331 product summary page search advanced | parametric | part number | faq select country motorola home | semiconductors home | contact us semiconductors products | design support | register | login motorola > semiconductors > mc68331 : 32 bit microcontroller the mc68331 is a highly-integrated 32 bit microcontroller that combines high-performance data manipulation capabilities with powerful peripheral subsystems.this mcu is built up from standard modules that interface through a common intermodule bus (imb). the mcu incorporates a 32 bit cpu (cpu32), a system integration module (sim), a general purpose timer (gpt) and a queued serial module (qsm). mc68331 features l modular architecture l central processing unit (cpu32) l upward object code compatible l new instructions for controller applications l 32 bit archirecture l virtual memory implementation l loop mode of insruction execution l table lookup and interpolate instruction l improved exception handling for controller applications l trace on change of flow l hardware breakpoint signal, background debugging mode (bdm) l fully static operation return to top page contents: features documentation tools orderable parts related links other info: faqs 3rd party design help training 3rd party tool vendors 3rd party trainers rate this page -- - 0 + ++ care to comment? mc68331 documentation documentation application note id name vendor id format size k rev # date last modified order availability an1051/d transmission line effects in pcb applications motorola pdf 1534 0 1/01/1990 an1200/d an1200/d configuring the m68300 family time processing unit(tpu) motorola pdf 1078 0 1/01/1991 an1230/d an1230/d a background debugging mode driver package for modular microcontrollers motorola pdf 177 0 1/01/1996 an473/d an473/d a minimum evaluation system for the mc68331 and mc68332 motorola pdf 264 0 1/01/1990 m68331_332tut/d an introduction to the mc68331 and mc68332 motorola pdf 287 0 1/01/1996 - brochure id name vendor id format size k rev # date last modified order availability cfpitchpak 68k coldfire product portfolio motorola html 1 0 10/14/2002 file:///f|/imaging/bitting/cf_process/cpl/11252003/moto/mc68331ts.htm (1 of 6) [28-nov-03 5:29:47 pm]
mc68331 product summary page data sheets id name vendor id format size k rev # date last modified order availability mc68331ts/d 68331 technical summary motorola pdf 440 2 1/01/1996 mc68331um/d 68331 users manual (technical data) motorola pdf 1366 0 1/01/1996 - engineering bulletin id name vendor id format size k rev # date last modified order availability eb253/d how to use the table lookup and interpolate instruction on the cpu32 motorola pdf 64 0 1/01/1999 eb256/d use of the lock bit on modular microcontrollers with flash eeprom motorola pdf 19 0 1/01/1999 eb257/d detecting loss of clock on modular microcontrollers motorola pdf 14 0 1/01/1999 eb258/d sources of reset on modular microcontrollers motorola pdf 25 0 1/01/1999 eb259/d why mc68300 and mc68hc16 mcus may halt after the release of reset motorola pdf 20 0 1/01/1999 eb260/d why an mc68300 or mc68hc16 microcontroller may fail to release reset motorola pdf 24 0 1/01/1999 eb261/d autovector generation using chip select logic on mc68300 and mc68hc16 devices motorola pdf 25 0 1/01/1998 eb262/d dsack generation on the system integration and single- chip integration motorola pdf 27 0 1/01/1998 eb263/d how to program chip selects on modular microcontrollers with a system integration module or a single-chip integration module motorola pdf 45 0 1/01/1998 eb264/d disabling all interrupts on power-on for mc683xx and mc68hc16 devices using the single-chip integration module or system integration module motorola pdf 28 0 1/01/1998 eb265/d generating edge-sensitive interrupts on the mc683xx and mc68hc16 families of mcus motorola pdf 27 0 1/01/1998 eb266/d unexplained three-stating of the address bus on m68300 and m68hc16 devices motorola pdf 26 0 1/01/1999 eb267/d the double bus fault monitor motorola pdf 27 0 1/01/1998 eb269/d using the sci on modular mcus: an example motorola pdf 33 0 1/01/1999 eb273/d which pins on the mc68331/332 and mc68hc16z1 need pullup resistors motorola pdf 29 0 1/01/1998 eb274/d generating interrupts on the time processor unit motorola pdf 18 0 1/01/1999 eb275/d example using the queued serial peripheral interface on modular mcus motorola pdf 48 0 1/01/1999 eb276/d using the itc function on the time processor unit a motorola pdf 27 0 1/01/1999 eb277/d coherency in the time processor unit (tpu) motorola pdf 26 0 1/01/1998 eb279/d low output levels on output pins motorola pdf 27 0 1/01/1998 eb281/d halting and re-starting the queued serial peripheral interface on modular microcontrollers motorola pdf 24 0 1/01/1999 eb305/d startup problems when using a software background mode debugger and booting from ram or an empty rom socket motorola pdf 18 0 1/01/1999 file:///f|/imaging/bitting/cf_process/cpl/11252003/moto/mc68331ts.htm (2 of 6) [28-nov-03 5:29:47 pm]
mc68331 product summary page eb310/d using bus error stack frames to diagnose cpu32 released write faults motorola pdf 47 0 1/01/1999 eb314/d updating the software watchdog on m683xx and mc68hc16 products motorola pdf 40 0 1/01/1999 errata - click here for important errata information id name vendor id format size k rev # date last modified order availability mc68331mse1/d mc68331 device information sheet: e95b-f43e mask sets motorola pdf 39 1 3/26/1998 - mc68331mse2/d mc68331 device information sheet: 01g91h mask sets motorola pdf 24 1 11/20/1996 - mc68331mse3/d mc68331 device information sheet: 00h17a mask sets motorola pdf 15 1 3/26/1998 - product change notices id name vendor id format size k rev # date last modified order availability pcn3787 lea ronal plating - pcn3787 motorola txt 42 - 8/28/1998 - pcn7717 update to gpcn#7622 besd end of life motorola htm 2 - 7/05/2002 - pcn7720 adendum to:motorola besd end of life buy motorola htm 4 - 7/05/2002 - pcn7917 20x20 lqfp assy move from shc to klm motorola htm 24 0 8/19/2002 - pcn8158 mc68331 and mc68332 mos12 qualification motorola htm 16 0 11/05/2002 - reference manual id name vendor id format size k rev # date last modified order availability adcrm/ad analog-to-digital reference manual motorola pdf 231 0 1/01/1996 cpu32rm/ad cpu32 reference manual motorola pdf 1467 0 1/01/1996 ctmrm/ad configurable timer module reference manual motorola pdf 565 0 1/01/1998 - gptrm/ad general-purpose timer reference manual motorola pdf 447 0 1/10/1995 mccirm/ad mccirm multi-channel communications interface reference manual motorola pdf 968 1 8/31/2001 mpc500_m68300_cd_zip motorola automotive high performance microcontroller documentation cd: mpc500 and m68300 motorola zip 81132 0 10/15/2000 - qadcrm/d queued analog-to-digital converter reference manual motorola pdf 730 0 1/01/1996 - qsmrm/ad qsmrm qsm queued serial module reference manual motorola pdf 1298 0 1/01/1996 simrm/ad simrm system integration module reference manual motorola pdf 1168 0 1/10/1999 roadmap id name vendor id format size k rev # date last modified order availability coldfirerd coldfire performance roadmap motorola pdf 79 0 10/23/2002 - file:///f|/imaging/bitting/cf_process/cpl/11252003/moto/mc68331ts.htm (3 of 6) [28-nov-03 5:29:47 pm]
mc68331 product summary page selector guide id name vendor id format size k rev # date last modified order availability sg1001 32-bit embedded processors - quarter 4, 2003 motorola pdf 877 1 11/07/2003 sg1006 microcontrollers selector guide - quarter 4, 2003 motorola pdf 826 0 10/24/2003 sg1011 software and development tools selector guide - quarter 4, 2003 motorola pdf 287 0 10/24/2003 sg187 automotive selector guide - quarter 4, 2003 motorola pdf 1916 14 10/24/2003 users guide id name vendor id format size k rev # date last modified order availability m68331bcc/d m68331bcc m68331bcc business card computer users manual motorola pdf 194 0 10/01/1993 - m68331evk/d m68331evk m68331evk evaluation kit users manual motorola pdf 293 1 10/01/1993 - m68mpb331um/d m68mpb331 m68mpb331 mcu personality board users manual motorola pdf 334 1 3/01/1998 - return to top mc68331 tools hardware tools emulators/probes/wigglers id name vendor id format size k rev # order availability serialdebugsdi development tools motorola - - - - hmi-200-cpu32 hmi-200-cpu32 in-circuit emulator avocet - - - - hmi-bmd-cpu32-l hmi-bmd-cpu32-l background mode debugger avocet - - - - hmi-usb-bmd-cpu32 hmi-usb-bmd-cpu32 background mode debugger avocet - - - - ic20000 ic2000 poweremulator isys - - - - ic30001 ic3000 activeemulator isys - - - - ic40000 ic4000 activeemulator isys - - - - evaluation/development boards and systems id name vendor id format size k rev # order availability mevb1632 68hc16, 68300 development tools motorola - - - - 00010 generic 683xx development board ash ware - - - - 10 generic 683xx development board ash ware - - - - file:///f|/imaging/bitting/cf_process/cpl/11252003/moto/mc68331ts.htm (4 of 6) [28-nov-03 5:29:47 pm]
mc68331 product summary page software application software monitor code id name vendor id format size k rev # order availability cpu32bugfw cpu32bug monitor motorola zip 221 - - operating systems id name vendor id format size k rev # order availability cmx-rtx cmx-rtx cmx - - - - protocol stacks id name vendor id format size k rev # order availability cmx tcp/ip cmx tcp/ip cmx - - - - software tools assemblers id name vendor id format size k rev # order availability as32v1-2asm dos based freeware assembler motorola zip 50 - - adx-68k adx-68k macro assembler-linker and ide avocet - - - - ax68300 ax68300 relocatable and absolute macro assembler for 68300 and 68k cosmic - - - - compilers id name vendor id format size k rev # order availability cx68300 cx68300 c cross compiler for 68300/68k cosmic - - - - diab diab c/c++ compiler windriv - - - - debuggers id name vendor id format size k rev # order availability bd32-122dbg background debug monitor for 68300 parts motorola zip 88 - - zap 68300 icd zap 68300 bdm debugger cosmic - - - - zap 68300 sim zap 68300/68k simulator debugger cosmic - - - - emulation id name vendor id format size k rev # order availability 00003 tpu standard mask simulator ash ware - - - - 00004 tpu simulator ash ware - - - - 3 tpu standard mask simulator ash ware - - - - 4 tpu simulator ash ware - - - - ide (integrated development environment) id name vendor id format size k rev # order availability idea68300 idea68300 - integrated development environment for 68300/68k cosmic - - - - ic-sw-opr winidea isys - - - - return to top orderable parts information file:///f|/imaging/bitting/cf_process/cpl/11252003/moto/mc68331ts.htm (5 of 6) [28-nov-03 5:29:47 pm]
mc68331 product summary page partnumber package info tape and reel life cycle description (code) budgetary price qty 1000+ ($us) additional info order availability mc68331cfc16 pqfp 132 0.950*.950p.025 no product maturity/saturation(4) $10.21 more mc68331cfc16b1 pqfp 132 0.950*.950p.025 no product maturity/saturation(4) $9.83 more mc68331cfc20 pqfp 132 0.950*.950p.025 no product maturity/saturation(4) $10.71 more mc68331cfc20b1 pqfp 132 0.950*.950p.025 no product maturity/saturation(4) $10.31 more mc68331cfc25 pqfp 132 0.950*.950p.025 no product maturity/saturation(4) $11.22 more mc68331cfc25b1 pqfp 132 0.950*.950p.025 no product maturity/saturation(4) $10.80 more mc68331cpv16 lqfp 144 20*20*1.4p0.5 no product maturity/saturation(4) $8.30 more MC68331CPV16B1 lqfp 144 20*20*1.4p0.5 no product maturity/saturation(4) $7.90 more mc68331cpv20 lqfp 144 20*20*1.4p0.5 no product maturity/saturation(4) $8.71 more mc68331cpv20b1 lqfp 144 20*20*1.4p0.5 no product maturity/saturation(4) $8.29 more mc68331cpv25 lqfp 144 20*20*1.4p0.5 no product maturity/saturation(4) $9.13 more mc68331mfc16 pqfp 132 0.950*.950p.025 no product maturity/saturation(4) $11.22 more mc68331vfc16 pqfp 132 0.950*.950p.025 no product maturity/saturation(4) $10.71 more note: are you looking for an obsolete orderable part? click here to check our distributors' inventory. return to top related links 68k/coldfire? microcontrollers motor control tpu microcoding made easy book return to top http://www.motorola.com/ | site map | contact motorola | terms of use | privacy practices ? copyright 1994-2003 motorola, inc. all rights reserved. file:///f|/imaging/bitting/cf_process/cpl/11252003/moto/mc68331ts.htm (6 of 6) [28-nov-03 5:29:47 pm]

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